Method for testing a memory chip in multiple passes

Details Method for testing a memory chip in multiple passes Method for testing a memory chip in multiple passes

1998-03-31

1999-11-23

Nelms, David

Static information storage and retrieval

Read/write circuit

Testing

371 211, G11C 700, G11C 2900

Patent

active

059912154

ABSTRACT:
A method of testing and diagnosing memory arrays. The method efficiently identifies a memory chip having faulty memory cells, and subsequently removes the memory chip containing the faulty memory cells from the testing process. The method uses a testing module and an active parts list. The method uses the active parts list to contain an identifier for each of a plurality of memory modules which do not have any identified malfunctioning memory cells.

REFERENCES:
patent: 3644899 (1972-02-01), Boisvert, Jr.
patent: 3681757 (1972-08-01), Allen et al.
patent: 3758759 (1973-09-01), Boisvert, Jr. et al.
patent: 4066880 (1978-01-01), Salley
patent: 4379259 (1983-04-01), Varadi et al.
patent: 4456995 (1984-06-01), Ryan
patent: 4918693 (1990-04-01), Ardini, Jr. et al.
patent: 5654204 (1997-08-01), Anderson
patent: 5794175 (1998-08-01), Conner
patent: 5796246 (1998-08-01), Poh et al.
patent: 5805472 (1998-09-01), Fukasawa
patent: 5828223 (1998-10-01), Rabkin et al.
patent: 5841785 (1998-11-01), Suzuki
patent: 5862146 (1999-01-01), Chen et al.

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