Error detection/correction and fault detection/recovery – Pulse or data error handling – Error/fault detection technique
Reexamination Certificate
2005-03-15
2005-03-15
Chase, Shelly A (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Error/fault detection technique
C714S746000
Reexamination Certificate
active
06868522
ABSTRACT:
A communication module coding a first original header signal as a first check signal by a first coding means, and outputs an output header signal by whitening the first original header signal and the first check signal with a clock code according to a second coding means. A method for the communication module includes obtaining the output header signal; generating a guessing clock code; dewhitening the output header signal into a second original header signal and a second check signal by a third decoding means with the guessing clock code; utilizing the first coding means to form a third check signal from the second original header signal; and comparing the third check signal to the second check signal. The third decoding means decodes the output header signal into the first original header signal and the first check signal while the guessing clock code is substantially the same as the clock code.
REFERENCES:
patent: 5052026 (1991-09-01), Walley
patent: 6543022 (2003-04-01), O'Connor
Dr. Bernd X. Weis, Cell alignment in ATM systems via header error check: performance evaluation had hardware considerations, Mar. 1990, IEEE, pp. 115-130.
Chen Yi-Ching
Hsu Da-Jin
Shih Chien-Yi
Chase Shelly A
Hu Winston
VIA Technologies Inc.
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