Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1998-06-16
2002-03-26
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06363520
ABSTRACT:
The present invention relates to method of producing a synthesizable Register Transfer (RT) Level VHDL specification for input to a synthesis tool to generate a gate-level circuit having testability enhancement.
BACKGROUND OF THE INVENTION
VLSI circuit complexity has made testing difficult and more expensive. Increasing the testability of a design becomes one of the important issues in the design cycle of VLSI circuits. It helps to achieve the high test quality and to reduce test development and test application costs. In the past, it was possible to add Design-for-Testability (DFT) circuits manually after logic synthesis. But current needs for a shorter time to market makes this approach an unaffordable design bottleneck. Ignoring DFT during the design cycle affects product quality and introduces schedule delays. Most industrial digital designs use automated synthesis and DFT can be achieved by incorporating test and synthesis into a single methodology that is as automated as possible. Indeed, considering testability during the design synthesis, as opposed to traditional approaches of making back-end modification after an implementation has been generated, can reduce design time. Even more important, the testability enhancement at the entry level to a synthesis tool makes it independent of the tool and the implementation technology. It becomes part of the design specification.
As indicated below, several methods have been proposed in the literature to address the problem of testability analysis at higher levels of abstraction. Most of them concentrate on improving the testability of datapaths, assuming that the controller can be tested independently and that its outgoing control signals to the datapath are fully controllable in test mode. However, even when both the controller and the datapath are individually testable, the composite circuit may not be. A method based on testability analysis at the behavioural level was presented in C. Papachristou and J. Carletta, “Test Synthesis in the Behavioural Domain”, IEEE International Test Conference, 1995, pp. 693, 702. While the authors perform the test insertion of the datapath at the behavioural level, test point insertion for the controller and the interface between the datapath and the controller, is performed at the structural level. Moreover, even if the authors use two metrics for testability analysis at the behavioural level, test overhead can be very large for practical circuits. In contradistinction, the present invention considers the Controllability and the Observability of each bit of each signal and/or variable declared in the VHDL specification after data type conversion. In addition, test point insertion is also performed at the bits of each signal and/or variable identified as hard to detect areas instead of all bits, as used in previous methods (see for example P. Vishakantaiah et al., “Automatic Test Knowledge Extraction from VHDL (ATKET)”, IEEE Design Automation conference, pp. 273-278); X. Gu, et al., “Testability Analysis and Improvement from VHDL behavior Specification”, Proc. EURO-DAC, pp. 644-649, 1994; A. Debreil, P. Oddo, “Synchronous Designs in VHDL’, Euro-VHDL 93, pp. 486-491, and this can reduce the test overhead for practical circuits and makes test point insertion more oriented to the hardware represented by the VHDL specification.
Another method which considers testability features at the behavioral level was presented in X. Gu, et al., “Testability Analysis and Improvement from VHDL behavior Specification”, Proc. EURO-DAC, pp. 644-649, 1994. However, the paper analyzes only very simple VHDL constructs to perform test point insertion at the RT-Level. In addition, the TM computations based on Controllability and Observability transfer functions are very complex for large primitive functional modules and involve more hardware for test point insertion.
Other methods (see S. Dey and M. Potkonjak, “Transforming Behavioural Specifications to Facilitate Synthesis of Testable Designs”, ITC pp. 184-193, 1994; P. Vishakantaiah et al, “AMBIANT: Automatic Generation of Behavorial Modifications for Testability”, IEEE ICCD, pp. 63-66, October 1993; A. Debreil, P. Oddo, “Synchronous Designs in VHDL’, Euro-VHDL 93, pp. 486-491) work by modifying a behavioral description before high level synthesis begins, however they concentrate on the testability of the synthesized datapath, without outlining a test scheme for testing the datapath and the controller as a whole.
Finally, recently an RT-Level testability analysis method has been proposed in W. Mao and R. K. Gulati, “Improving Gate-Level Fault coverage by RTL Fault Grading”, ITC pp. 463-472, 1996. The authors use verilog RT-Level models and functional verification patterns to evaluate the fault coverage of the resulting circuit. However, the paper does not propose test point insertion at the RT-Level to improve the testability of the resulting circuit.
SUMMARY OF THE INVENTION
The primary objective of the method of the present invention is to raise the level of abstraction at which testability analysis and test point insertion is performed. The present invention proposes a new testability analysis and test point insertion method at the RT-level assuming full scan and a Built In Self Test (BIST) design environment. The method uses as the starting point a specification given at the synthesizable RT-Level VHDL. The specification is analyzed to produce an intermediate representation, called the VHDL Intermediate Format (VIF), and transformed into a Directed Acyclic Graph (DAG) on which testability analysis is performed by computing and propagating Testability Measures (TMs) forward and backward through the VHDL statements. These measures are then used to identify the bits of each signal and/or variable on which faults are hard to detect. Finally, test point insertion is performed to improve testability, again at the RT-Level, by adding new VHDL test statements.
The computation of Controllability and Observability method is purely functional, that is, it does not subsume the knowledge of a gate-level implementation of the circuit being analyzed. Therefore, it enables the computation of testability estimations with a high degree of accuracy for circuits on which existing tools fail due to the enormous amount of information which must be handled when considering the structural implementation of the circuit.
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Boubezari Samir
Cerny Eduard
Kaminska Bozena
Nadeau-Dostie Benoit
LogicVision, Inc.
Sheridan & Ross P.C.
Smith Matthew
Thompson A. M.
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