Method for synchronizing data with a bi-directional buffer

Electrical computers and digital processing systems: support – Clock control of data processing system – component – or data...

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710129, G06F 112

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active

060292539

ABSTRACT:
A bi-directional buffer circuit for transferring data between clock boundaries in a computer system is described. The circuit is divided into halves, with one half being controlled by a first clock and the second half being controlled by a second clock. The incoming data that is synchronized to the first clock is compiled into data blocks and stored into registers before being synchronized and transferred to the other half of the circuit. The data blocks that are stored in the register sent across a the clock boundary the then synchronized into matched registers within the second half of the circuit. In addition, the signals that control the synchronization of data blocks between the halves of the circuit are synchronized by two stages of registers to avoid the problem of metastability.

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