Method for synchronizing clocks upon reset

Details Method for synchronizing clocks upon reset Method for synchronizing clocks upon reset

1994-07-11

1996-04-23

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

327141, 327115, H03K 513

Patent

active

055107400

ABSTRACT:
A synchronized clocking circuit receives a clock signal and, in accordance with the received clock signal, provides a divided-down clock signal having a known phase relationship with respect to the received clock signal upon reset. In order to provide the known phase relationship, and therefore to synchronize the received clock signal and the divided-down clock signal, a cycle of the divided down clock signal is selectably skipped. A reset signal is conditioned and applied to an active going edge detector. The cycle of the divided down clock is selectably skipped according to the active going edge detector.

REFERENCES:
patent: 4356566 (1982-10-01), Wada et al.
patent: 4361895 (1982-11-01), Khoudari
patent: 4516861 (1985-05-01), Frew et al.
patent: 4709160 (1987-11-01), Kinoshita
patent: 4758737 (1988-07-01), Hirano
patent: 4847516 (1989-07-01), Fujita et al.
patent: 5111150 (1992-05-01), Casey

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