Method for switching between multiple system processors

Details Method for switching between multiple system processors Method for switching between multiple system processors

1998-05-14

2000-10-24

Beausoliel, Jr., Robert W.

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

714 11, 714 56, G06F 1100

Patent

active

061382477

ABSTRACT:
In a method for switching between multiple system processors (152,172) on a CompactPCI bus (110,120), when a standby system processor (172,152) determines a failure affecting an active system processor (152,172) on the CompactPCI bus (110,120), the standby system processor (172,152) places a special arbiter (820) in a one master mode. If the standby system processor (172,152) determines that a device is at risk of performing a destructive action, the standby system processor (172,152) quiesces the device. The standby system processor (172,152) then places the special arbiter (820) in a multiple master mode.

REFERENCES:
patent: 5434998 (1995-07-01), Akai
patent: 5500945 (1996-03-01), Maeda
patent: 5627965 (1997-05-01), Liddell
patent: 5991900 (1999-11-01), Garnett
"Finite States Machine That Allows a Soft (recoverable) Stop of a processor System That has a Memory Subsystem that Cannot Be Halted." IBM TDB vol. 33, No. 3A, pp. 340-342, Aug. 1, 1990.
Booklet entitled "CompactPCI Specification" by PCI Industrial Computers (Sep. 2, 1997).

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