Semiconductor device manufacturing: process – Making passive device – Stacked capacitor
Reexamination Certificate
2001-12-13
2003-09-02
Cuneo, Kamand (Department: 2829)
Semiconductor device manufacturing: process
Making passive device
Stacked capacitor
C438S689000, C438S757000
Reexamination Certificate
active
06613642
ABSTRACT:
BACKGROUND
The present invention relates generally to semiconductor device processing and, more particularly, to methods of enhancing the surface of devices, such as capacitors, used in computer memory systems.
Modem dynamic random access memories (DRAMs) commonly use a single capacitor as a data storage element. As the packing density of DRAMs continues to increase over time, the size of the individual transistors and capacitors within an individual memory cell have correspondingly decreased. However, as the dimensions of the capacitors decrease, so too will the capacitance values associated therewith if no additional measures are taken.
In order for a DRAM memory cell to operate reliably, the capacitor therein should have a relatively large capacitance value so that the capacitor is less likely to be affected by noise or by the parasitic capacity of the metal lines and wires. Accordingly, a capacitor having an increased surface area is commonly used to maintain a sufficient capacitance value. Nevertheless, even with the use of deep trench capacitors or stacked capacitors, the available device cell area continues to shrink and, as a result, the capacitance value is difficult to maintain.
Given a limited amount of lateral width and vertical depth or height available for capacitors, another existing approach to maintaining the necessary capacitance values has been to increase the surface area of the capacitor without increasing the lateral or vertical dimensions of the capacitor itself. For example, hemispherical grains (HSG) of silicon may be attached to the surfaces of the capacitor. However, while this process may result in increased surface area and hence increased capacitance, it typically requires specialized tools for the implementation thereof. Furthermore, there is an inherent risk of capacitor leakage associated with this process, due to the use of non-crystalline silicon.
BRIEF SUMMARY
The foregoing discussed drawbacks and deficiencies of the prior art are overcome or alleviated by a method for increasing the surface area of an original surface in a semiconductor device. In an exemplary embodiment of the invention, the method includes forming a layered mask upon the original surface, the layered mask including a masking layer thereatop having a varying thickness. An isotropic etch is then applied to the layered mask, which isotropic etch further removes exposed portions of the original surface as the layered mask is removed. Thereby, the isotropic etch creates a non-uniformity in planarity of the original surface.
In a preferred embodiment, the method further includes forming a silicon layer upon the original surface, and then forming the masking layer upon the silicon layer. The silicon layer and the masking layer are included within the layered mask. The isotropic etch is then applied to both the masking layer and the silicon layer, with the isotropic etch enhancing the varying thickness and further removing the exposed portions of the original surface as the silicon layer is removed. The silicon layer is etched at a faster rate than the masking layer, which masking layer further comprises a nitride layer.
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Jammy Rajarao
Kudelka Stephan
McStay Irene
Rahn Stephen
Schroeder Uwe
Blecker Ira D.
Cantor & Colburn LLP
International Business Machines - Corporation
Sarkar Asok Kumar
LandOfFree
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