Static information storage and retrieval – Systems using particular element – Ferroelectric
Reexamination Certificate
2001-06-28
2002-12-24
Nelms, David (Department: 2818)
Static information storage and retrieval
Systems using particular element
Ferroelectric
C365S189090
Reexamination Certificate
active
06498743
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field of the Invention
The present invention relates to a method for supplying a reference potential to a sense amplifier circuit in a semiconductor integrated circuit that is equipped with a memory cell including a capacitor as a charge storage capacitor and a switch element as a transfer gate, a semiconductor integrated circuit, a semiconductor device equipped with many of the semiconductor integrated circuits, and an electronic apparatus using the semiconductor device, and more particularly to a technology to control the timing for supplying a reference potential to a sense amplifier circuit at the time of data reading.
2. Conventional Technology
A conventional semiconductor integrated circuit structure equipped with capacitors having ferroelectric bodies and their operation are shown in a block diagram in FIG.
6
and in a timing chart shown in
FIG. 7
, respectively.
First, the circuit structure shown in
FIG. 6
is described. As being well known, memory cells
1
~
4
arranged side by side include, as their components, capacitors
9
,
10
,
11
and
12
as charge storage capacitors formed from ferroelectric bodies, and Nch transistors
5
,
6
,
7
and
8
as transfer gates for switching the capacitors, respectively. With a sense amplifier
13
for reading data being at the center, each of the memory cells
1
and
2
is connected to the sense amplifier
13
through a bit line BLR on the right side of the sense amplifier
13
, and is also connected to a plate line PLR on the right side. On the other hand, each of the memory cells
3
and
4
is connected to the sense amplifier
13
through a bit line BLL on the left side, and is also connected to a plate line PLL on the left side. Gates of the Nch transistors
5
,
6
,
7
and
8
of the memory cells are connected to corresponding independent word lines WL
1
R, WL
2
R, WL
1
L and WL
2
L, respectively. Each of the bit lines BLR and BLL is connected to one of the source/drain of each of the Nch transistors
15
and
16
, respectively. The other of the source/drain of each of the Nch transistors
15
and
16
is grounded, and gates thereof are connected to signal lines for providing pre-charge signals PRC.
The sense amplifier
13
receives an input of a sense amplifier drive signal SA and outputs data read out from each of the memory cells. A reference potential VREF is inputted in the sense amplifier
13
from a reference potential generation circuit
14
through the Nch transistors
17
and
18
. Gates of the Nch transistors
17
and
18
connect to signal lines that transfer reference potential application signals REFL and REFR, respectively.
Also, a block selection circuit
19
outputs a block signal BLK to selectively switch between a group of the signal lines on the right side to be driven (WL
1
R, WL
2
R, PLR, REFR) and a group of the signal lines on the left side (WL
1
L, WL
2
L, PLL, REFL), and to select among the memory cells
1
~
4
that are subject to a reading operation or a writing operation.
Next, a reading operation is described with reference to FIG.
6
and FIG.
7
.
FIG. 5
is a timing chart of a reading operation. For example, when the memory cell
1
is read, the pre-charge signal PRC is lowered from the power supply potential VDD to the GND potential, and then the block signal BLK is elevated to the power supply potential VDD. Subsequently, the reference potential application signal REFR is elevated, then, the bit line BLL is charged to the reference potential VREF because the Nch transistor
18
is turned on, such that the bit line BLR retains the GND potential (in an open state). Next, the GND potential on the word line WL
1
R is set to the power supply potential VDD, to thereby put the transistor
5
in an ON state. Subsequently, when the GND potential on the cell plate line PLR is set to the power supply potential VDD, a potential corresponding to a charge (data) associated with a polarization retained in the ferroelectric capacitor
9
is generated on the bit line BLR. Here, when the reference potential VREF is set at a value intermediate the bit line potentials that are to be generated respectively corresponding to H level and L level of data, the sense amplifier
13
detects and amplifies the magnitude of the potential, such that data corresponding to H level or L level of memory cell data are outputted. It is noted that, in here, WL
1
L, WL
2
L, PLL and REFL are fixed at the GND potential by the BLK signal.
In the conventional semiconductor integrated circuit, as shown in
FIG. 7
, the timing to turn on the sense amplifier
13
(the timing at which the sense amplifier drive signal SA is elevated to the power supply potential VDD) must be set, in theory, at least after t
3
. In addition, in practice, a response delay in the detection sensitivity of the sense amplifier, a delay time in which AV (a potential difference on the bit line BLR, BLL with respect to the reference potential VREF) becomes sufficiently large, and the like have to be considered. Therefore, the timing to turn on the sense amplifier
13
has to be set in a period after t
4
. For this reason, a fatal problem as a memory device, namely, slow reading speed, has not been overcome.
The present invention solves the problem described above, and its object is to quicken the timing to apply a reference potential to be supplied to a sense amplifier, to thereby quicken the on-timing of the sense amplifier, and to improve the reading speed.
SUMMARY OF THE INVENTION
In a method for supplying a reference potential to a sense amplifier in a semiconductor integrated circuit in accordance with the present invention, a method is provided for supplying a reference potential to a sense amplifier in a semiconductor integrated circuit equipped with a memory cell including a capacitor composing a ferroelectric body that stores data depending on a polarization state determined by an applied voltage and a direction of the voltage, a sense amplifier circuit that reads out data from the memory cell, and a reference potential generation circuit that generates a reference potential for the sense amplifier circuit, wherein, when the data is read from the ferroelectric body, a reference potential from the reference potential generation circuit is supplied to the sense amplifier circuit based on a signal that drives a cell plate that composes one of the electrodes of the capacitor.
Also, in a semiconductor integrated circuit in accordance with the present invention, the semiconductor integrated circuit reads the data from the ferroelectric body by the method for supplying a reference potential described above, and is equipped with a memory cell including a capacitor composing a ferroelectric body that stores data depending on a polarization state determined by an applied voltage and a direction of the voltage, a sense amplifier circuit that reads out data from the memory cell, and a reference potential generation circuit that generates a reference potential for the sense amplifier circuit.
Furthermore, in a semiconductor integrated circuit in accordance with the present invention, the semiconductor integrated circuit is equipped with a memory cell including a capacitor composing a ferroelectric body that stores data depending on a polarization state determined by an applied voltage and a direction of the voltage, a sense amplifier circuit that reads out data from the memory cell, and a reference potential generation circuit that generates a reference potential for the sense amplifier circuit, wherein a plate line is connected to a cell plate that composes one of the electrodes of the capacitor for transmitting a drive signal for reading out the data, and wherein a switch element is interposed in a supply path for supplying the reference potential between the reference potential generation circuit and the sense amplifier circuit, wherein the switch element is connected to the plate line, and is placed in an ON state upon receiving the drive signal that is transmitted to the plate line, and the reference potential is
Harness, Dickey & Pierce P.L.C
Le Thong
Nelms David
Seiko Epson Corporation
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