Method for stress testing decoders and periphery circuits

Details Method for stress testing decoders and periphery circuits Method for stress testing decoders and periphery circuits

1993-04-30

1994-08-23

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Testing

36518905, 36523008, G11C 700

Patent

active

053413369

ABSTRACT:
A method for stress testing decoders and other periphery circuits used with a memory array. An address buffer simultaneously sets the inputs of a plurality of decoders to a first common voltage level, so that a plurality of rows and/or columns within the memory array are selected for a predetermined period of time. A stress voltage is then applied to the integrated circuit to stress test the gate oxides within the decoders and other periphery circuits. The inputs of the plurality of decoders are then simultaneously set to a second common voltage level, so that the plurality of rows and/or columns within the memory array are deselected. Finally, a stress voltage is applied to the integrated circuit to stress test the gate oxides within the decoders and other periphery circuits.

REFERENCES:
patent: 4651304 (1987-03-01), Takata
patent: 5208776 (1993-05-01), Nasu et al.

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