Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2003-01-09
2004-11-16
Lam, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S201000
Reexamination Certificate
active
06819606
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a method for storing data and a device for storing data, and relates in particular to a method for storing data in a memory device having memory cells arranged in memory cell rows and memory cell columns, system defects brought about by defective memory cells being eliminated.
BACKGROUND ART
During the conception, the design and the construction of memory modules it is unavoidable that system failures brought about by defective memory cells will occur during the operating time of a memory module, i.e. while the memory module is in an active state in a circuit.
In this case, the exact construction of a memory module is insignificant, so that memory modules are hereinafter referred to quite generally as “memory devices”. Due to the increasing complexity of electronic circuits and the continuously increasing integration density of circuit units (“chips”), system failures of this type result for example from problems in the reliability of the memory module, brought about by electromigration, etc.
Many electronic systems in which memory units are arranged react very sensitively to an occurrence of memory cell defects, so that the requirements made of reliability and availability of memory units also increase as integration density increases. Due to the increasing complexity of electronic circuit units, it is necessary to effect a trade off between an efficiency of a circuit design and a conception of the hardware to be created. Existing hardware concepts require that they can be used in different circuit environments, even when defective memory cells occur.
FIG. 2
shows a timing diagram of a conventional sequence when a memory cell defect occurs in a conventional memory device. In
FIG. 2
, a reference symbol
201
designates a conventional system availability, which can vary between 0% and 100%.
A time axis
202
(“Time”) designates different points in time and is arranged on a scale such that it is possible to represent a time progression from an occurrence of a memory cell defect
203
up to the end of a booting operation
207
. Conventionally, the entire system has to be switched off when a memory cell defect
203
occurs, so that a beginning
204
of a system failure results directly after an occurrence of a memory cell defect
203
.
The consequence of conventional system failures is that a system availability
201
falls from 100% (assuming that no further defects occurred) to 0%. Finally, the defective hardware is exchanged, which is expensive and time-consuming particularly in the case of complex electronic systems. A reference symbol
206
specifies a so-called memory exchange time duration.
After the memory exchange time duration
206
has elapsed, the total system failure ends, i.e. the conventional system availability
201
rises again slowly, proceeding from 0%. After a booting time duration
208
, the full (100%) conventional system availability
201
is reached again at the end
207
of the booting operation.
Consequently, one disadvantage of conventional methods for eliminating a memory defect is that a long system failure time occurs, which, with reference to
FIG. 2
, occurs as a sum of the memory exchange time duration
206
and the booting time duration
208
.
A further disadvantage of conventional methods for recovering a system availability
201
is that exchanging defective hardware or switching off the entire system is expensive and impracticable, under certain circumstances, since total system failures are to be avoided.
SUMMARY OF THE INVENTION
Consequently, it is an object of the present invention to provide a method for storing data in a memory device in which defective memory cells of a memory unit are replaced by redundant memory cells during the operating time of a memory.
The redundant memory cells are expediently accessed in such a way that a system restart or system booting is avoided.
This object is achieved according to the invention by means of the method specified in patent claim
1
and by means of a memory device having the features of patent claim
9
.
Further refinements of the invention emerge from the subclaims.
An essential concept of the invention consists in a system availability being completely or at least partly maintained when a defect occurs in memory cells, in that redundant memory cells present in the memory device undertake the function of defective memory cells.
Thus, one advantage of the present invention is that a system availability (this is possibly slightly reduced) can be maintained even when defects occur in memory cells.
Moreover, it is expedient that the method according to the invention advantageously utilizes effectively always existing redundant memory cells, thereby enabling economical circuit development.
In particular, in the case of a system failure caused by defective memory cells, it is not necessary to exchange system components. In this way, no additional hardware costs arise and a cost-efficient procedure in the case of memory cell defects is achieved.
Furthermore, one advantage of the method according to the invention is that the time of reduced system availability is reduced, so that replacement of defective memory cells can be performed in a short time during operation of the memory unit.
The invention's method for storing data in a memory device having memory cells arranged in memory cell rows and memory cell columns, system defects brought about by defective memory cells being eliminated, essentially has the following steps:
a) provision of redundant memory cells present in the memory device;
b) provision of a predeterminable access mode for accessing the redundant memory cells; and
c) replacement of defective memory cells of the memory device by the redundant memory cells in a manner dependent on the predetermined access mode during operation of the memory device.
Advantageous developments and improvements of the respective subject matter of the invention can be found in the subclaims.
In accordance with one preferred development of the present invention, replacement of the defective memory cells of the memory device by the redundant memory cells is provided in a reversible fashion. It is expediently possible for already allocated redundant memory cells which have replaced defective memory cells to be provided with other defective memory cells of the memory device.
In accordance with yet another preferred development of the present invention, a predeterminable number of redundant memory cell rows or a predeterminable number of redundant memory cell columns are provided.
It is thus possible, in an advantageous manner, that, if a defective memory cell occurs in the memory device, the system can determine whether a corresponding memory cell row or a corresponding memory cell column is used for the replacement of the defective memory cell or the defective memory cells.
In a further expedient manner, replacement may be provided by programming a register which, by way of example, comprises both an activation bit and the defective column or row address.
In accordance with yet another preferred development of the present invention, defective memory cells of the memory device are replaced by an exchange of at least one memory cell row and/or at least one memory cell column in a manner dependent on the predetermined access mode during operation of the memory device.
In accordance with yet another preferred development of the present invention, an exchange of defective memory cells of the memory device is carried out in a manner dependent on the predetermined access mode during operation of the memory device by programming an access register, an activation bit and at least one address of the memory cell row and/or the memory cell column which are/is to be replaced advantageously being provided.
In accordance with yet another preferred development of the present invention, the predeterminable access mode for accessing the redundant memory cells during operation of the memory device is provided by a test mode of the memory device.
In accordance with yet anot
Benedix Alexander
Dankowski Stefan
Dueregger Reinhard
Ruf Wolfgang
Infineon - Technologies AG
Jenkins & Wilson & Taylor, P.A.
Lam David
LandOfFree
Method for storing data in a memory device with the... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for storing data in a memory device with the..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for storing data in a memory device with the... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3276503