Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Having air-gap dielectric
Reexamination Certificate
2005-07-19
2005-07-19
Deo, Duy-Vu N. (Department: 1765)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Having air-gap dielectric
C438S424000, C438S717000, C438S719000, C438S723000, C438S724000
Reexamination Certificate
active
06919259
ABSTRACT:
A method for dry etching a feature to control an etching depth using endpoint detection and a sacrificial hardmask including providing a substrate for etching a feature opening into said substrate, said substrate provided with at least a first dielectric layer overlying the substrate; providing at least a second dielectric layer including a sacrificial hardmask at a predetermined thickness over the at least a first dielectric layer; photolithographically patterning and etching in a first dry etching process through a thickness of the at least a second dielectric layer and the at least a first dielectric layer to expose the substrate for dry etching the feature opening; and, dry etching in a second dry etching process the substrate and the sacrificial hardmask layer to endpoint detection of an underlying layer with respect to the sacrificial hardmask layer to thereby etch through a predetermined thickness of the substrate.
REFERENCES:
patent: 5413966 (1995-05-01), Schoenborn
patent: 5994201 (1999-11-01), Lee
patent: 6057208 (2000-05-01), Lin et al.
patent: 6140206 (2000-10-01), Li et al.
patent: 2003/0104675 (2003-06-01), Lim et al.
Chang Yao-Chi
Lu Jeff
Deo Duy-Vu N.
Taiwan Semiconductor Manufacturing Co. Ltd
Tung & Associates
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