Method for static timing verification of integrated circuits...

Details Method for static timing verification of integrated circuits... Method for static timing verification of integrated circuits...

2006-01-24

2006-01-24

Whitmore, Stacy A. (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

Reexamination Certificate

active

06990645

ABSTRACT:
A method of analysis of an integrated circuit design having multiple voltage islands, including: (a) determining a clock path through the voltage islands; (b) determining a data path through the voltage islands; (c) determining which voltage islands are independent voltage islands; (d) determining which voltage islands are dependent voltage islands; (e) for the data path and the clock path, performing a worst case static timing analysis based on minimum and maximum operating voltages of each independent and dependent voltage island in the data and clock paths; and (f) for the data path and the clock path, performing a best case static timing analysis based on minimum and maximum operating voltages of each independent and dependent voltage island in the data and clock paths.

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Cheng et al., Use of “Slack ” as a Measurement of Being Time and the Procedure for Calculating Slack, IBM Technical Disclosure Bulletin, vol. 25, No. 6, Nov. 1982., pp. 2826-2830.

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