Method for stacking semiconductor chips

Details Method for stacking semiconductor chips Method for stacking semiconductor chips

2007-09-26

2009-06-16

Thai, Luan C (Department: 2891)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S668000, C257S774000, C257S773000, C257S621000, C257S686000, C257SE23174, C257SE23145

Reexamination Certificate

active

07547630

ABSTRACT:
In a semiconductor system (100) including a chip (101) and a workpiece (102), the chip has metal-filled vias (140) positioned between contact pads (120) and the respective edges (110). In addition, seals against microcracks (150) and thermo-mechanical stress (151) are located between the vias and the active components, and sometimes also between the vias and the respective nearest edge. Workpiece (102) may be another semiconductor chip or a substrate; it has contact pads (170) matching the locations of the vias (140). The chip is vertically stacked on the workpiece so that each contact pad (170) is aligned and in electrical contact with the corresponding via (140).

REFERENCES:
patent: 6608371 (2003-08-01), Kurashima et al.
patent: 6703689 (2004-03-01), Wada
patent: 7180149 (2007-02-01), Yamamoto et al.
patent: 7335972 (2008-02-01), Chanchani

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