Method for stacking and interconnecting integrated circuits

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material

Reexamination Certificate

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Details

C438S109000, C257SE23067, C257SE23174

Reexamination Certificate

active

08034713

ABSTRACT:
A method for stacking and interconnecting integrated circuits includes providing at least two substrates; forming a trench in each substrate; filling the trench with an insulating material; forming, in each substrate, at least one conductive area; thinning each substrate until reaching at least the bottom of the trench, to obtain in each substrate at least one electrically insulated region within the closed perimeter delineated by the trench; bonding the substrates together; making at least one hole through the bonded substrates so that the hole passes at least partially through the conductive areas and passes through the insulated region of each substrate; and filling the hole with an electrically conductive material so as to obtain a conductive column that traverses the isolated region of each substrate and is in lateral electrical contact with the conductive areas.

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patent: 6642081 (2003-11-01), Patti
patent: 7786587 (2010-08-01), Hoshino et al.
patent: 2002/0017710 (2002-02-01), Kurashima et al.
patent: 2002/0135062 (2002-09-01), Mastromatteo et al.
patent: 2005/0101054 (2005-05-01), Mastromatteo et al.
patent: 2008/0203556 (2008-08-01), Huang
patent: 2009/0134527 (2009-05-01), Chang
patent: 2002-050736 (2002-02-01), None
patent: 99/56508 (1999-11-01), None

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