Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1997-06-23
2000-07-18
Chan, Eddie P.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711129, G06F 1200
Patent
active
060921528
ABSTRACT:
The present invention includes methods for caching method frames using multiple stack cache management units to provide access to multiple portions of the method frames. In some embodiments of the invention, a first frame component of a first method frame is cached in a first stack cache management unit. A second frame component of the first method frame is cached in a second stack cache management unit. In addition, a first frame component of a second method frame is also cached in the second stack cache management unit and a second frame component of the second method frame is cached in the first stack cache management unit. The first frame components of the method frames can be, for example, operand stacks of the method frames. The second frame components of the method frames can be, for example, the arguments and local variable areas of the method frames.
REFERENCES:
patent: 3810117 (1974-05-01), Healey
patent: 3878513 (1975-04-01), Werner
patent: 3889243 (1975-06-01), Drimak
patent: 3924245 (1975-12-01), Eaton et al.
patent: 4268903 (1981-05-01), Miki et al.
patent: 4354232 (1982-10-01), Ryan
patent: 4375678 (1983-03-01), Krebs, Jr.
patent: 4524416 (1985-06-01), Stanley et al.
patent: 4530049 (1985-07-01), Zee
patent: 4600986 (1986-07-01), Sheuneman et al.
patent: 4674032 (1987-06-01), Michaelson
patent: 4761733 (1988-08-01), McCrocklin et al.
patent: 4811208 (1989-03-01), Myers et al.
patent: 4951194 (1990-08-01), Bradley et al.
patent: 5043870 (1991-08-01), Ditzel et al.
patent: 5093777 (1992-03-01), Ryan
patent: 5107457 (1992-04-01), Hayes et al.
patent: 5142635 (1992-08-01), Saini
patent: 5157777 (1992-10-01), Lai et al.
patent: 5210874 (1993-05-01), Karger
patent: 5485572 (1996-01-01), Overly
patent: 5535350 (1996-07-01), Maemura
patent: 5603006 (1997-02-01), Satake et al.
patent: 5634027 (1997-05-01), Saito
patent: 5636362 (1997-06-01), Stone et al.
patent: 5687336 (1997-11-01), Shen et al.
patent: 5784553 (1998-07-01), Kolawa et al.
Electronic Engineering, vol. 61, No. 750, Jun. 1989, p. 79, XP000033120, "Up Pops A 32Bit Stack Microprocessor".
Atkinson, R.R., et al., "The Dragon Processor", Second International Conference on Architectural Support for Programming Languages and Operating Systems, No. 1987, Oct. 5, 1987, pp. 65-69, XP000042867.
Stanley, et al., "A Performance Analysis of Automatically Managed Top of Stack Buffers", 14th Annual International Symposium on Computer Architecture, Jun. 2, 1987, pp. 272-281, XP002032257.
Burnley, P: "CPU Architecture for Realtime VME Systems", Microprocessors and Microsystems, London, GB, vol. 12, No. 3; Apr. 1988; pp. 153-158; XP000002633.
Lopriore, L: "Line Fetch/Prefetch in a Stack Cache Memory",Microprocessors and Microsystems, vol. 17, No. 9, Nov. 1, 1993, pp. 547-555, XP00413173.
Microsoft Press Computer Dictionary, 2.sup.nd Ed., p. 279, 1994.
O'Connor James Michael
Tremblay Marc
Chan Eddie P.
McKay Philip J.
McLean Kimberly
Sun Microsystems Inc.
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