Semiconductor device manufacturing: process – Forming bipolar transistor by formation or alteration of... – Self-aligned
Reexamination Certificate
2002-12-18
2004-04-27
Le, Dung A. (Department: 2818)
Semiconductor device manufacturing: process
Forming bipolar transistor by formation or alteration of...
Self-aligned
C438S303000, C438S766000
Reexamination Certificate
active
06727155
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to a method for forming sidewall spacers on a semiconductor substrate and more particularly, relates to a method for forming sidewall spacers of a dielectric material on a silicon wafer by spin etching with an acid vapor such that plasma damages to the silicon substrate can be avoided.
BACKGROUND OF THE INVENTION
Modern semiconductor devices are built on semi-conducting substrates such as silicon substrates that have P
+
and N
+
type doped regions in the substrates as basic elements of the device. These doped regions must be connected in a specific configuration to form a desired circuit. The circuit needs to be accessible to the outside world through conducting pads for testing and through bonding into a packaged chip. To form a semiconductor circuit, at least one layer of a conducting material such as metal must be deposited and patterned to form contacts and interconnects between the different regions of the chip. For instance, in a typical semiconductor fabrication process, a silicon wafer is first covered with an insulating layer and then, patterned and etched for contact openings in the insulating layer. A conductive material is then deposited and defined to form contact plugs and interconnecting leads.
On top of a silicon wafer, semiconductor gates are normally formed of a polysilicon material with a thin gate oxide layer in-between the polysilicon gate and the silicon substrate. A typical semiconductor gate structure
10
is shown in
FIGS. 1A and 1B
. In order to insulate the polysilicon gate
12
, a silicon oxide layer
14
or any other dielectric material layer such as silicon nitride or silicon oxynitride is deposited on top. A thick silicon oxide layer of several thousand angstrom thickness can be deposited by a rapid thermal chemical vapor deposition (RTCVD) technique. In the process for forming the sidewall spacers
16
from the dielectric layer
14
, it is important that the material deposited, i.e. silicon oxide, must have both a high deposition rate such that a thick layer can be deposited in a short period of time and a good conformability such that the polysilicon gate can be completely covered. For instance, when silicon oxide is deposited, the TEOS (tetra-ethoxy-silane) chemistry can be used at a high deposition temperature of 800° C. for achieving a deposition rate of about 1000 Å/min. The high deposition rate satisfies a throughput requirement for the semiconductor device. The high deposition temperature limits the deposition process to the front end of the semiconductor fabrication wherein metal wiring layers are not involved.
After the conformal deposition of the silicon oxide layer
14
to approximately 5000-8000 Å thickness, a reactive ion etching (RIE) method is used to pattern the gate sidewall spacers
16
. The RIE technique is chosen since the anisotropic plasma used in the technique is effective in forming the sidewall spacers
16
on the gate
12
. In the RIE technique, positive plasma ions in a parallel-plate RF reactor are used to provide a source of energetic particle bombardment for the etched surface, producing vertical edges in the etched film with negligible undercutting. The ion bombardment increases the reaction rate of spontaneously occurring processes and prompts reactions which do not occur without radiation. In a typical reactive ion etching system, the wafers are placed on the powered electrode of a parallel-plate RF reactor wherein horizontal surfaces are subjected to both reactant species and impinging ions, while vertical sidewalls are only subjected to reactive species.
In the conventional method of patterning sidewall spacers by the reactive ion etching method, it has been discovered that the plasma ions bombarded during the etching process damage the silicon surface at the source/drain area that will enhance dark current (or leakage current) and impact the signal
oise ratio of a photoelectronic device. As shown in
FIG. 1E
, a surface layer
18
of the silicon substrate
20
in the source/drain area
22
,
24
is frequently damaged by the plasma ions which severely affects the reliability of the device fabricated.
It is therefore an object of the present invention to provide a method for forming sidewall spacers on a polysilicon gate without the drawbacks or shortcomings of the conventional reactive ion etching method.
It is another object of the present invention to provide a method for forming sidewall spacers on a polysilicon gate that does not cause plasma damages in the source/drain area of the silicon substrate.
It is a further object of the present invention to provide a method for forming sidewall spacers on a polysilicon gate without using reactive ion etching or plasma etching for patterning the spacers.
It is another further object of the present invention to provide a method for forming sidewall spacers on a polysilicon gate by utilizing a spin mode acid vapor etching technique.
It is still another object of the present invention to provide a method for forming sidewall spacers on a polysilicon gate by flowing an acid vapor onto a semiconductor wafer while spinning the wafer at a rotational speed of at least 50 rpm.
It is yet another object of the present invention to provide a method for etching dielectric spacers on a silicon substrate without causing plasma damages to the substrate by utilizing a spin mold acid vapor etching technique.
It is still another further object of the present invention to provide a method for etching dielectric spacers on a silicon substrate without causing plasma damages to the substrate by first annealing and densifying the dielectric material before subjecting the substrate to an acid vapor while being rotated at a speed of at least 50 rpm.
It is yet another further object of the present invention to provide a method for etching dielectric spacers on a silicon substrate without causing plasma damages to the substrate wherein the spacers are formed of SiO
2
, SiON or Si
3
N
4
and the acid vapor is HF, H
3
PO
4
, H
2
SO
4
or HCl.
SUMMARY OF THE INVENTION
In accordance with the present invention, a method for forming sidewall spacers on a semiconductor substrate or a method for etching dielectric spacers on a silicon substrate without causing plasma damages to the silicon substrate is provided.
In a preferred embodiment, a method for forming sidewall spacers on a semiconductor substrate can be carried out by the operating steps of first providing a semiconductor substrate that has a gate structure formed on top; depositing a dielectric material layer on top of the semiconductor substrate; rotating the semiconductor substrate to a rotational speed of at least 50 rpm; and flowing an acid vapor onto the semiconductor substrate until the sidewall spacers are formed.
The method for forming sidewall spacers on a semiconductor substrate may further include the step of mounting the semiconductor substrate on a wafer chuck situated in a spin etcher. The dielectric material layer may be formed of a material selected from the group consisting of SiO
2
, SiON and Si
3
N
4
. The semiconductor substrate may be a silicon wafer, and the gate structure may be formed for a photoelectronic device. The method may further include the step, subsequent to the deposition step, of annealing the semiconductor substrate at a temperature of at least 700° C. for a time period of at least 10 min. The method may further include the step of annealing the semiconductor substrate at a temperature between about 700° C. and about 800° C. for a time period between about 10 min. and about 20 min. after the depositing step. The method may further include the step of flowing an acid vapor formed of an acid selected from the group consisting of HF, H
3
PO
4
, H
2
SO
4
and HCl onto the semiconductor substrate. The method may further include the step of rotating the semiconductor substrate to a rotational speed between about 50 rpm and about 200 rpm. The method may further include the step of rotating the semiconductor substrate to a ro
Chnug Chaucer
Huang Yuan-Chang
Yang Jiunn-Der
Le Dung A.
Taiwan Semiconductor Manufacturing Co. Ltd.
Tung & Associates
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