Electrical computers and digital processing systems: memory – Address formation – Combining two or more values to create address
Patent
1997-04-04
1999-11-02
Lane, Jack A.
Electrical computers and digital processing systems: memory
Address formation
Combining two or more values to create address
711214, G06F 934, G06F 935
Patent
active
059788950
ABSTRACT:
Method and apparatus are disclosed for increasing the speed of mathematical operations in a processor core. The invention increases the speed of mathematical operations by delivering a first instruction indicating the total number of clock cycles a sequence of operations will occupy. On a first subsequent cycle, a different instruction is provided including operand addresses. Other instructions containing operand addresses may be provided on subsequent cycles. Alternatively, an internal pointer may be dynamically changed each cycle to provide new operand addresses. The operands are then retrieved and operated on while other operands are generated.
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Cirrus Logic Inc.
Lane Jack A.
Shaw Steven A.
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