Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-12-11
2003-08-12
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06606732
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to the manufacturing of integrated circuits (ICs) on semiconductor wafers, and, in particular, to the design and configuration of signal wires for differential pairs on ICs.
2. Description of Related Art
In computer packages, limited interconnection resources are required to make connections to inputs and outputs on differential current switch (DCS) logic elements. The interconnection resources may be wiring pins, vias, wiring tracks or other interconnection resources that are limited in number or by physical or design restrictions. The limited resources must be assigned to respective requirements so as to globally optimize their use. DCS logic elements uses differential signal pairs to represent logic signals (i.e., 1 or 0) and requires two inputs for each basic logic switch. The DCS logic switch uses a pair of transistors that steer current in one of two directions to define the binary state of the switch, and has two inputs to each logic gate, connected to the bases of the two transistors. To change the state of the DCS logic element, one of the inputs is driven high and the other is simultaneously driven low.
When selecting signal wires for differential pairs on IC packages, a number of criteria need to be considered, among them, adjacency of controlled collapsed chip connections (C4s) or wire bond pads which electrically connect individual chips in a multichip module (MCM) or package, adjacency of electrically connecting pins, balls or columns which connect the MCM or package to a substrate, and adjacency of package redistribution wires and vias in the package substrate. Additional criteria include the closeness of total wire length, resistance, inductance, capacitance, and time of flight (IRLCTf) values (i.e., time for a signal to pass from one end of a wiring net to the other), identicalness of in-MLC redistribution layers for the escape wires, and specific voltage references of the redistribution layers for the escape wire. Differential in-package wire pairs become important as there are more and more “differential signals”.
Currently, differential wire pairs are not clearly specified. It is up to the designer to first define what it means by ‘adjacency’, ‘closeness’, ‘identicalness’ and ‘specific’ in the above criteria, and then search, by hand, for possible nets that could be considered differential wire pairs. The definition of ‘adjacency’, ‘closeness’, ‘identicalness’ and ‘specific’ may be different depending on the stringency placed on the design. Also, there is no tool that checks that the differential pairs selected are legal differential pairs, according to the criteria.
Bearing in mind the problems and deficiencies of the prior art, it is therefore an object of the present invention to provide an improved method of selecting differential pairs in computer packages incorporating differential switch logic elements.
It is another object of the present invention to provide a method of automating the design of differential wire pairs in integrated circuit packages.
It is a further object of the present invention to provide a method of standardizing criteria for specifying, identifying, selecting and verifying differential signal pairs on IC packages.
Still other objects and advantages of the invention will in part be obvious and will in part be apparent from the specification.
SUMMARY OF THE INVENTION
The above and other objects and advantages, which will be apparent to one of skill in the art, are achieved in the present invention which is directed to, in a first aspect, an automated method of selecting differential pairs in an integrated circuit comprising loading the design database for the integrated circuit package, and selecting output parameters for the differential pairs comprising adjacency criteria for the different pairs, time of flight tolerances for the differential pairs, and the redistribution layers and their voltage references. The method then includes comparing the output parameters to the design in the design database, and obtaining a resulting differential pairs list. The differential pair list preferably includes differential signal pairs having electrical characteristics within a predetermined design tolerance range. At least some of the differential signal pairs may comprise individual wires or connectors not physically adjacent one another.
The differential pair list may include bundles of differential signal pairs having electrical characteristics within a predetermined design tolerance range, and at least some of the differential signal pairs in the bundles may be differential signal pairs not physically adjacent one another. The differential pair list may include groups of differential signal pairs having electrical characteristics within a predetermined design tolerance range, and at least some of the differential signal pairs in the groups may be bundles of differential signal pairs not physically adjacent one another. The method may further include obtaining a table of resistance, inductance and capacitance values of each differential signal pair.
In another aspect, the present invention provides a system for selecting differential pairs in an integrated circuit comprising means for loading the design database for the integrated circuit package, and means for selecting output parameters for the differential pairs comprising adjacency criteria for the different pairs, time of flight tolerances for the differential pairs, and the redistribution layers and their voltage references. The system also includes means for comparing the output parameters to the design in the design database, and means for obtaining a resulting differential pairs list.
In a further aspect, the present invention relates to an article of manufacture comprising a computer usable medium having computer readable program code means embodied therein for selecting differential pairs in an integrated circuit. The article comprises computer readable program code means for loading the design database for the integrated circuit package, and computer readable program code means for selecting output parameters for the differential pairs comprising adjacency criteria for the different pairs, time of flight tolerances for the differential pairs, and the redistribution layers and their voltage references. The article further includes computer readable program code means for comparing the output parameters to the design in the design database, and computer readable program code means for obtaining a resulting differential pairs list.
Another aspect of the present invention relates to a program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine to perform method steps for selecting differential pairs in an integrated circuit. The method steps comprise loading the design database for the integrated circuit package, and selecting output parameters for the differential pairs comprising adjacency criteria for the different pairs, time of flight tolerances for the differential pairs, and the redistribution layers and their voltage references. The method then includes comparing the output parameters to the design in the design database, and obtaining a resulting differential pairs list.
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Buffet Patrick H.
Lussier Craig
Natonio Joseph
Curcio Robert
DeLio & Peterson LLC
Dinh Paul
International Business Machines - Corporation
Kotulak Richard M.
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