Method for soft error modeling with double current pulse

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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C716S030000, C257S297000

Reexamination Certificate

active

07627840

ABSTRACT:
A method of modeling soft errors in a logic circuit uses two separate current sources inserted at the source and drain of a device to simulate a single event upset (SEU) caused by, e.g., an alpha-particle strike. In an nfet implementation the current flows from the source or drain toward the body of the device. Current waveforms having known amplitudes are injected at the current sources while simulating operation of the logic circuit and the state of the logic circuit is determined from the simulated operation. The amplitudes of the current waveforms can be independently adjusted. The simulator monitors the state of device and makes a log entry when a transition occurs. The process may be repeated for other devices in the logic circuit to provide an overall characterization of the susceptibility of the circuit to soft errors.

REFERENCES:
patent: 6330182 (2001-12-01), Zhang
patent: 6348356 (2002-02-01), Shabde et al.
patent: 6928626 (2005-08-01), McGaughy et al.
patent: 7322015 (2008-01-01), Liu et al.
patent: 2008/0077376 (2008-03-01), Belhaddad et al.
U.S. Appl. No. 11/355,342, Acar, et al.

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