Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
2006-01-17
2006-01-17
Peugh, Brian R. (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C711S162000, C711S146000
Reexamination Certificate
active
06988166
ABSTRACT:
To implement a RAID 1 transaction, an initiator sends a single command, i.e., either a single read command, or a single write command, over a common I/O bus to a primary target device. A mirror target device snoops the common I/O bus and upon detecting the single command directed to the primary target device, effectively performs in the same manner as if the command had been directed to the mirror target device. Hence, a single command is used to effectuate a mirrored transaction.
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patent: 2003/0014520 (2003-01-01), Rinaldis et al.
Sahai, “Performance Aspects of RAID Architectures”, © 1997 IEEE, p. 321-327.
Adaptec, Inc.
Gunnison Forrest
Gunnison McKay & Hodgson, L.L.P.
Peugh Brian R.
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