Method for sloping the sidewalls of multilayer P+ PN+ junction m

Details Method for sloping the sidewalls of multilayer P+ PN+ junction m Method for sloping the sidewalls of multilayer P+ PN+ junction m

1975-09-19

1977-06-14

Van Horn, Charles E.

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

156657, 156662, 252 793, H01L 21306

Patent

active

040295427

ABSTRACT:
A method for insuring that the sidewall of a P+ PN+ layered junction mesa semiconductor structure is tapered smoothly from the P layer to the N+ layer of the structure upon formation thereof by immersion of a wafer comprised of the structure in an etchant of 3% HF and 97% HNO.sub.3, comprising the steps of placing an etch mask dot having a diameter slightly less than the greatest diameter required for the N+ layer above the P+ layer at a preselected site on the wafer, preselecting a specific ratio of etchant quantity to P silicon quantity, immersing the wafer in the preselected quantity of the etchant, and withdrawing the wafer from the etchant at the instant at which the silicon is removed from around the dot.

REFERENCES:
patent: 3007830 (1961-11-01), Bardsley
patent: 3607480 (1971-09-01), Harrap et al.
patent: 3811974 (1974-05-01), Squillace et al.
patent: 3894895 (1975-07-01), Khandelwal

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