Method for skipping a latch in timing-sensitive dynamic...

Details Method for skipping a latch in timing-sensitive dynamic... Method for skipping a latch in timing-sensitive dynamic...

1999-11-08

2004-05-18

Le, Don (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

C326S121000

Reexamination Certificate

active

06737888

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates generally to staged circuits and, more specifically, to staged circuits, which use multi-clocks for timing.
2. Description of Related Art
It has been well known in the art to process data signal inputs in a first stage of a multi-stage circuit and then use the output from the first stage as an input for a subsequent stage. While dynamic circuit applications are known wherein each stage is clocked using a single clock, multi-clock systems are well known. In a typical multi-clock system, a first stage receives first inputs for processing, which are clocked using a first clock. The output of the first stage is fed to the input of a second stage, which is processed using a second clock.
Generally, for the second or later stages of such a design to work, the reset of the previous stage driven by its clock must be slow enough, so that the previous stage outputs are held as the inputs on a subsequent stage long enough for the circuit to properly evaluate.
FIG. 1
is a schematic of a multi-stage circuit having first and second stages being controlled by first and second clocks. In the depicted figure, two stage circuit
100
includes four P-FETs (P-channel Field Effect Transistors), transistors P
102
, P
104
, P
106
, and P
108
, as well as three N-FETs (N-channel Field Effect transistors), N
102
, N
104
, and N
106
. Each stage contains a logic device, one of devices L
102
and L
104
, and a pair of inverters, I
102
and I
104
or I
106
and I
108
. Stage
1
comprises logic device L
102
being connected to drains of transistors P
102
and N
102
, respectively, where clock C
1
is fed to the transistors' gates. The drain of transistor P
102
is connected to an output port of logic device L
102
. The drain of transistor P
102
is further connected to the inputs of inverters I
102
and I
104
and the drain of transistor P
104
. The output of inverter I
102
feeds to the gate of transistor P
104
whose drain is tied to the inputs of inverters I
102
and I
104
.
The output of inverter I
104
provides input signal O
1
for the stage
2
, including logic device L
104
. The remainder of stage
2
is similar to that of stage
1
, comprising logic device L
104
being connected to drains of transistors P
106
and N
104
, respectively, where clock C
2
is fed to the transistors' gates. The drain of transistor P
106
being connected to an output port of logic device L
104
and is further connected to the inputs of inverters I
106
and I
108
. The output of inverter I
106
feeds the gates of transistors P
108
and N
106
whose drains are tied to the inputs of inverters I
106
and I
108
and to the output port of logic device
104
. The evaluation results from logic device
104
are inverted by inverter I
108
, and then output from stage
2
.
Dual clock circuit
100
depicted in
FIG. 1
is for use in applications in which the two clocks (C
1
and C
2
) are not underlapped. The design shown in
FIG. 1
assumes that the clocks are not underlapped. In other words, C
1
rises at the same time C
2
falls and more importantly for the second stage, C
2
rises and the same time that C
1
falls. In the case where this relationship cannot be guaranteed (but the clocks are guaranteed to be underlapped), extra logic must be added so that the outputs of the C
1
stage are stable for the inputs of the C
2
stage. This extra logic poses performance and stability problems for the system.
It would be advantageous to deal with the underlap condition without adding extra logic to the system.
SUMMARY OF THE INVENTION
The present invention relates to a means for solving the undeterminable clock underlap problem associated with multi-stage, multi-clock circuits. The first stage of the multi-stage circuit utilizes a first clock for outputting a signal to the second stage. However, rather than relying on the first clock for triggering both the rising edge and the falling edge of the output, the first stage utilizes a second clock for triggering the falling edge of the output. The second clock also controls the second stage output. In a preferred embodiment of the present invention, this occurs because the first clock stage will not reset until both the first clock is low and second clock are high due to the addition of the second clock signal. The duration of the control clock signal used for controlling the first stage output is increased from an interval defined by the duration of the first clock to an interval defined by the duration of the first clock combined with the inverted second clock signal. The clock falling edge, which triggers the falling edge of the output now becomes the inverted rising edge of the second clock. In accordance with a preferred embodiment, this is accomplished by adding a transistor and inverter to the first stage. The drain of a P-type FET is connected to the source of the P-FET being controlled by the first clock through its gate. The additional P-FET is controlled by an inverted second clock signal, the clock signal being inverted by an inverter connected to the gate of the additional P-FET.
Stability is provided to the first stage by creating a full keeper, which holds the evaluation results from the logic device in the first stage. A pair of transistors are connected by their drains to the evaluation results output of the logic device. The transistors are controlled by an inverter, which is connected to the pair's bases, wherein the inverter receives the evaluation results. The transistor pair comprises one N-FET and P-FET.


REFERENCES:
patent: 5378942 (1995-01-01), Wu et al.
patent: 5453708 (1995-09-01), Gupta et al.
patent: 5825208 (1998-10-01), Levy et al.
patent: 5880608 (1999-03-01), Mehta et al.
patent: 6040716 (2000-03-01), Bosshart

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