Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Patent
1999-04-28
2000-09-26
Thomas, Tom
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
438396, 438399, 438239, 438241, 438253, 257239, 257396, H01H 214763
Patent
active
061241997
ABSTRACT:
A DRAM memory cell array includes a wiring layer formed at a storage-capacitor level of the cell for establishing a flipped connection of complementary bit lines, or for connecting support circuits in a DRAM cell array. The wiring layer includes a lower capacitor electrode and upper capacitor electrode which are formed simultaneously with respective plates of a storage capacitor. Both capacitor electrodes may be used to form distinct interconnections within a DRAM cell array.
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Bronner Gary B.
Gambino Jeffrey P.
Kotecki David E.
Radens Carl J.
International Business Machines - Corporation
Parekh Nitin
Petraske, Esq. Eric W.
Thomas Tom
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