Method for simultaneously fabricating a DRAM capacitor and metal

Details Method for simultaneously fabricating a DRAM capacitor and metal Method for simultaneously fabricating a DRAM capacitor and metal

1998-11-10

2000-06-06

Nguyen, Tuan H.

Semiconductor device manufacturing: process

Making passive device

Stacked capacitor

438256, 438399, H01L 2120

Patent

active

060717890

ABSTRACT:
A method for simultaneously forming a storage node and a plurality of interconnection in fabricating a semiconductor device on a substrate. The method comprises the steps of: forming a first dielectric layer over said cell array area and said periphery; forming a plurality of first contact holes through said first dielectric layer in said cell array area and said periphery area, said periphery area including a bitline and a word line, said word line and said bitline being used for addressing said memory cell; forming a first conductive layer in said plurality of first contact holes and on said first dielectric layer; patterning and etching said first conductive layer to form said storage node and said plurality of interconnections simultaneously; forming a second dielectric layer and a second conductive layer subsequently on said first dielectric layer, said storage node and said plurality of interconnections; and patterning and etching said second dielectric layer and said second conductive layer to form a charge storage means and a plurality of contact plugs.

REFERENCES:
patent: 5336632 (1994-08-01), Imamura
patent: 5674771 (1997-10-01), Machida et al.
patent: 5792681 (1998-08-01), Chang et al.
patent: 5879981 (1999-03-01), Tanigawa

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