Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Patent
1998-02-12
1999-12-21
Fahmy, Wael
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
438656, 438682, 438683, 438721, 438724, 257384, 257757, 257344, H01L 2144
Patent
active
060048786
ABSTRACT:
Sidewall spacers, adjacent a gate electrode and source/drain regions of a MOS transistor are formed of a dielectric material that can be etched selectively to the material selected as the isolation dielectric. A layer of silicide forming metal is deposited overlying the MOS transistor and heated, wherein silicide regions are formed where the metal makes contact with silicon, for example, in the gate electrode and source/drain regions. At least a portion of the sidewall spacers are etched-away and silicide stringers, if formed on the spacers, are removed.
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Daniels Brian J.
Thomas Michael E.
Coleman William David
Fahmy Wael
Kwok Edward D.
National Semiconductor Corporation
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