Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2007-07-17
2007-07-17
Bonzo, Bryce P (Department: 2113)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S011000
Reexamination Certificate
active
10347009
ABSTRACT:
An apparatus for and method of enhancing reliability within a cluster lock processing system having a relatively large number of commodity cluster instruction processors which are managed by a cluster lock manager. Because the commodity processors have virtually no system viability features such as memory protection, failure recovery, etc., the cluster/lock processors assume the responsibility for providing these functions. The low cost of the commodity cluster instruction processors makes the system almost linearly scalable. The cluster/locking, caching, and mass storage accessing functions are fully integrated into a single hardware platform which performs the role of the cluster/lock master. Upon failure of this hardware platform, a second redundant hardware platform converts from slave to master role. The logic for the failure detection and role swapping is placed within software, which can run as an application under a commonly available operating system. Furthermore, the recovery is completely accomplished without assistance of the Host computer(s) or ultimate user(s) coupled via the Host computer(s). Following repair of the failed server, it is restarted in an orderly fashion to resume a slave role. For the server to be completely restored, coherent memory must be copied from master to slave. Because cluster lock processing must be paused throughout the system to transfer the copy, it is important to minimize the transfer time to minimize the impact on system throughput.
REFERENCES:
patent: 5157663 (1992-10-01), Major et al.
patent: 5228127 (1993-07-01), Ikeda et al.
patent: 5530845 (1996-06-01), Hiatt et al.
patent: 5852724 (1998-12-01), Glenn et al.
patent: 5940826 (1999-08-01), Heideman et al.
patent: 5941999 (1999-08-01), Matena et al.
patent: 6145094 (2000-11-01), Shirriff et al.
patent: 6163856 (2000-12-01), Dion et al.
patent: 6223231 (2001-04-01), Mankude
patent: 6609213 (2003-08-01), Nguyen et al.
patent: 6625750 (2003-09-01), Duso et al.
patent: 6675217 (2004-01-01), Dani et al.
patent: 6883065 (2005-04-01), Pittelkow et al.
patent: 2002/0095470 (2002-07-01), Cochran et al.
patent: 2003/0158933 (2003-08-01), Smith
A. Butt, J. Hasan, K. Khalid, and F. Mirza, Economical Fault-Tolerant Networks, vol. 2000, Issue 74, Article No. 6, Jun. 2000.
Webopedia, “What is a Server?”, http://www. webopedia.com/TERM/c/server.html, Jul. 26, 2004, pp. 1-3.
Webopedia, “What is a computer?”, http://www.webopedia.com/TERM/c/computer.html, 2006, Jan. 4, 2002, 1-4.
Heideman Michael J.
Konrad Dennis R.
Novak David A.
Bonzo Bryce P
Johnson Charles A.
McMahon Beth L.
Nawrocki, Rooney & Sivertson P.A.
Unisys Corporation
LandOfFree
Method for shortening the resynchronization time following... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for shortening the resynchronization time following..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for shortening the resynchronization time following... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3770156