Semiconductor device manufacturing: process – Introduction of conductivity modifying dopant into... – Ion implantation of dopant into semiconductor region
Reexamination Certificate
1999-07-31
2001-03-13
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Introduction of conductivity modifying dopant into...
Ion implantation of dopant into semiconductor region
C438S519000, C438S525000, C438S527000, C438S531000, C257S404000, C257S408000, C430S311000, C430S313000, C430S314000, C216S067000, C216S079000
Reexamination Certificate
active
06200884
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to fabricating ultra-large scale integration (ULSI) semiconductor devices such as a ULSI metal oxide silicon field effect transistors (MOSFET), and more particularly to methods for improving the efficiency of high aspect ratio ion implantation in semiconductor fabrication.
BACKGROUND OF THE INVENTION
Semiconductor chips or wafers are used in many applications, including as processor chips for computers, and as integrated circuits and as flash memory for hand held computing devices, wireless telephones, and digital cameras. A common circuit component of semiconductor chips is the transistor. In ULSI semiconductor chips, a transistor is established by forming a polysilicon gate stack on a silicon substrate, and then forming a source region and a drain region in the substrate beneath the gate stack by implanting ion dopants into the areas of the substrate that are to become the source and drain regions. This generally-described structure cooperates to function as a transistor.
To shield the gate from the ions that are implanted to establish the source and drain regions, a photoresist mask is deposited over the areas sought to be shielded prior to ion implantation. Ions are then implanted in the areas between adjacent masked areas, often using what is referred to as “high aspect ratio” implantation in which the ions are directed almost vertically against the unshielded areas. High aspect ratio implantation is increasingly used mainly because the resist mask dimensions (i.e., a high aspect ratio space region) increasingly are smaller than they have been, to facilitate establishing more components on smaller chips. While for illustration purposes the above discussion considers ion implantation and photoresist gate masking in the transistor context, it is to be understood that the present invention is more widely directed to ion implantation in general.
It happens that the photoresist mask regions are formed with rectangular profiles. As understood herein, during ion implantation the top shoulders of the rectangular photoresist mask regions can block portions of the ion beam, particularly when a high aspect ratio is used to implant the ions. The present invention, having recognized the above-noted problem, provides the below-disclosed solutions, which also enhance device scaling in terms of process capability, since the present invention efficiently addresses any implantation process that requires high aspect ratio implantation.
BRIEF SUMMARY OF THE INVENTION
A method is disclosed for establishing an ion implantation region in a semiconductor substrate. The method includes forming plural mask regions over areas sought to be masked, and etching away top shoulders of the mask regions. Ions are then implanted at a high aspect ratio into areas between the mask regions.
In a preferred embodiment, the top shoulders, which initially are square, are etched away by directing plasma etchant against the mask regions to thereby round the shoulders. Non-reactive chemistry using Helium, Nitrogen, and/or Oxygen can be used to shape the shoulders, or reactive etch chemistry using Hydrogen Bromide with Oxygen (HBr/O
2
), or Chlorine with Oxygen (Cl
2
/O
2
), can be used. The etching act can be undertaken in a reactive ion etch chamber or a high density plasma chamber. A semiconductor device made according to the method, as well as a digital processing apparatus incorporating the semiconductor device, are also disclosed.
In another aspect, a method for making an ultra-large scale integration (ULSI) semiconductor device includes masking, with at least one resist layer, areas sought to be protected from ion implantation. This masking forms the aforementioned high aspect ratio space region. The method further includes shaping at least one shoulder of the resist layer to promote efficient ion implantation, then implanting ions into unmasked areas.
Other features of the present invention are disclosed or apparent in the section entitled “DETAILED DESCRIPTION OF THE INVENTION”.
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Chang Mark S.
Yang Chih-Yuh
Advanced Micro Devices , Inc.
Bowers Charles
LaRiviere Grubman & Payne, LLP
Sarkar Asok K.
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