Method for shaping features of a semiconductor structure using c

Details Method for shaping features of a semiconductor structure using c Method for shaping features of a semiconductor structure using c

1993-03-19

1994-04-12

Hearn, Brian E.

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

156662, 437228, 437249, 51281R, 51283R, H01L 21461

Patent

active

053022335

ABSTRACT:
In semiconductor manufacture a method of shaping the features of a semiconductor structure using chemical mechanical planarization (CMP) is provided. During CMP, a relatively soft polishing pad is utilized to conform to and contour a topography of the semiconductor structure. Another layer of a material such as a dielectric (e.g. TEOS based silicon dioxide) can then be deposited over the contoured topography without the inclusion of voids. The method of the invention is particularly suited to the formation of void free dielectric layers.

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H. Vora, Study of Mechano-Chemical Machining of Ceramics and the Effect of Thin Film Behavior, Honeywell, Feb. 1984, pp. 1-48.
W. L. C. M. Heyboer et al., "Chemomechanical Silicon Polishing", J. Electrochem. Soc., vol. 138, No. 3, Mar. 1991, pp. 774-777.
S. Wolf, Silicon Processing for the VLSI Era, vol. 2, Lattice Press, Sunset Beach, Calif. 1990, pp. 199-201, 232-239.

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