Semiconductor device manufacturing: process – Introduction of conductivity modifying dopant into... – Ion implantation of dopant into semiconductor region
Reexamination Certificate
2001-03-19
2002-09-17
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Introduction of conductivity modifying dopant into...
Ion implantation of dopant into semiconductor region
C438S257000
Reexamination Certificate
active
06451676
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a method for setting the threshold voltage in a MOS transistor, in particular during the fabrication of CMOS circuits.
A MOS (Metal Oxide Semiconductor) transistor is a field-effect transistor having an insulated control electrode or gate for controlling a current channel in a substrate. In this case, the charge carrier density in the semiconductor substrate is controlled by the voltage present at the gate terminal. If a sufficiently high voltage, which exceeds a specific threshold voltage, is applied to the gate electrode, an inversion current channel is produced at the semiconductor surface between the drain terminal and the source terminal of the MOSFET (Metal Oxide Semiconductor Field Effect Transistor), and a current can flow through the inversion current channel. The gate voltage, which is necessary to just form the inversion current channel, is referred to as the threshold voltage U
T
of the MOSFET. In CMOS (Complimentary Metal Oxide Semiconductor) technology, n-channel and p-channel MOS field-effect transistors are integrated simultaneously in the semiconductor substrate. In a conventional CMOS fabrication method, an n-type well, for example, is diffused into a p-conducting semiconductor substrate and a selective field oxidation is subsequently carried out in order to insulate the surfaces of the individual transistor regions from one another. A thin oxide layer is thereupon formed, which acts as a screen oxide or scatter oxide. The threshold voltages of the PMOS transistors and of the NMOS transistors are then set through the use of ion implantation. In a further process step, firstly the screen oxide is removed, then the gate oxide is produced and then polycrystalline silicon layers for the gate terminals are applied, and patterned, and, after electrical insulation of the gate stack from the drain and source regions through the use of a spacer, the diffusion of acceptors for the drain terminal and the source terminal of the PMOS transistor and a diffusion of donors for the drain terminal and source terminal of the NMOS transistor are carried out. After the contact windows have been opened by etching the drain and source regions, contacts can be made.
The coordination of the threshold voltage U
T
of the PMOS transistor and of the NMOS transistor complementary thereto in the CMOS circuit is of particular importance here since the threshold voltage of the two complementary transistors should be identical. The threshold voltage depends on the work function at the gate terminals. Work function refers to the energy required to release an electron from a crystal lattice. The gate electrodes are conventionally formed from crystalline polysilicon. The work function and thus the threshold voltage U
T
of the MOSFETs are in this case set by doping the polycrystalline silicon. By n-doping the gate electrode of the NMOS transistor and by p-doping the gate electrode of the PMOS transistor, the threshold voltages U
T
of the two complementary MOSFETs can be made the same in the conventional fabrication method. In this case, the threshold voltage U
T
typically lies between 0.5 volt and 0.7 volt.
The previous methods for setting the threshold voltages in NMOS transistors in CMOS fabrication technology have the disadvantage, however, that, on account of the different doping of the gate of the NMOS transistor and of the PMOS transistor, different dopants have to be provided and, furthermore, additional cost-intensive method steps for the masking and implantation of the different gate dopings are necessary.
A simpler and more cost-effective variant is to dope the polysilicon for both transistor types at an earlier point, for example when performing the deposition. A disadvantage is that the functionality of the “buried channel PMOS” is then reduced.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a simple method for setting the threshold voltage in MOS transistors which overcomes the above-mentioned disadvantages of the heretofore-known methods of this general type and which allows to accurately set the threshold voltage through the use of a very small number of process steps.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for setting a threshold voltage of a MOS transistor, the method includes the steps of:
providing a gate for a MOS transistor, the gate being formed of polysilicon; and
implanting germanium ions into the gate for changing a work function of the gate.
In other words, the invention provides a method for setting the threshold voltage in a MOS transistor having a gate composed of polysilicon, wherein germanium ions are implanted into the gate in order to change the work function of the gate composed of polysilicon.
Preferably, the gate implanted with germanium ions is subsequently heat-treated for annealing purposes or subjected to a thermal treatment by being exposed to a high temperature for a predetermined period of time.
This has the particular advantage that a crystalline gate structure is achieved.
In a particularly preferred mode of the invention, nitrogen ions are implanted into the gate composed of polysilicon before germanium ions are implanted.
This has the particular advantage that a thin layer composed of a silicon-nitrogen compound is formed between the gate and an underlying gate oxide, and prevents the formation of a germanium oxide layer.
Preferably, after the implantation of the nitrogen ions, the gate composed of polysilicon is heat-treated or subjected to thermal treatment for annealing purposes by being exposed to a high temperature for a specific period of time.
The method is preferably used for setting the threshold voltage of a PMOS transistor or an NMOS transistor in a CMOS circuit.
The temperature for thermal treatment of the gate after implantation is preferably above 1000° C.
The proportion of germanium which is implanted into the gate composed of polysilicon is preferably about 20%.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a method for setting the threshold voltage in MOS transistors, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.
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Curello Guiseppe
Wurzer Helmut
Dang Phuc T.
Greenberg Laurence A.
Infineon - Technologies AG
Locher Ralph E.
Nelms David
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