Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2009-09-17
2011-11-01
Booth, Richard A. (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S926000
Reexamination Certificate
active
08048790
ABSTRACT:
Semiconductor devices with replacement gate electrodes and integrated self aligned contacts are formed with enhanced gate dielectric layers and improved electrical isolation properties between the gate line and a contact. Embodiments include forming a removable gate electrode on a substrate, forming a self aligned contact stop layer over the removable gate electrode and the substrate, removing a portion of the self aligned contact stop layer over the removable gate electrode and the electrode itself leaving an opening, forming a replacement gate electrode of metal, in the opening, transforming an upper portion of the metal into a dielectric layer, and forming a self aligned contact. Embodiments include forming the contact stop layer of a dielectric material, e.g., a hafnium oxide, an aluminum oxide, or a silicon carbide and transforming the upper portion of the metal into a dielectric layer by oxidation, fluorination, or nitridation. Embodiments also include forming a hardmask layer over the removable gate electrode to protect the electrode during silicidation in source/drain regions of the semiconductor device.
REFERENCES:
patent: 6054355 (2000-04-01), Inumiya et al.
patent: 6080615 (2000-06-01), Lee et al.
patent: 6204137 (2001-03-01), Teo et al.
patent: 7091118 (2006-08-01), Pan et al.
patent: 2004/0175910 (2004-09-01), Pan et al.
Fastow, R. et al., A 45nm NOR Flash Technology with Self-Aligned Contacts and 0.024um2 Cell Size for Multi-level Applications, 2008, pp. 1-2, US.
Ishigaki, Y. et al., “Low Parasitic Resistance Technologies with NES-SAC and SWT-CVD Process for Low Supply Voltage, High Speed BiCMOS SRAMs”, Symposium on VLSI Technology Digest of Technical Papers, 1994, pp. 99-100, Japan.
Knorr Andreas
Soss Steven R.
Booth Richard A.
Ditthavong Mori & Steiner, P.C.
GLOBALFOUNDRIES Inc.
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