Method for self-aligned shallow trench isolation and method...

Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material

Reexamination Certificate

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C438S296000, C438S435000, C438S700000

Reexamination Certificate

active

06548374

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an isolation method and a method of manufacturing a semiconductor device comprising the same. More particularly, the present invention relates to a self-aligned shallow trench isolation (SA-STI) technique that simultaneously forms a gate and an active region, and a method of manufacturing a non-volatile memory device comprising the same.
2. Description of the Related Art
During the manufacture of memory devices, the packing density of cells is primarily determined by the layout of cells within the array and the physical dimensions of the cells themselves. Below the half-micron design rule, scalability of the layout is limited by photolithographic resolution attainable during manufacturing and by alignment tolerances of masks used during production. Alignment tolerances are, in turn, limited by mechanical techniques employed to form masks and the techniques use to register these masks between layers. Because alignment errors accumulate during multi-stage fabrication, it is preferable to use as few masks as possible. Fewer masks minimize the likelihood of misalignment. Accordingly, “self-alignment” processing steps have been developed to produce semiconductor devices.
Isolation structures between individual cells within the memory cell array consume regions of the chip that are otherwise useful for active circuitry. Thus, in order to increase the packing density of memory cell arrays within the substrate, it is desirable to minimize the size of these isolation structures. However, their process of formation and/or the alignment of the structures generally dictate the size of the isolation structure.
Typically, an isolation structure is grown at various regions of the chip by a thermal field oxidation process, such as a LOCal Oxidation of Silicon (hereinafter referred to as “LOCOS”). According to the LOCOS method, after a pad oxide layer and a nitride layer are successively formed, the nitride layer is subjected to patterning. Then, the patterned nitride layer is used as a mask to selectively oxidize the silicon substrate to form field oxide regions. However, in considering the LOCOS isolation, the growth of oxide may encroach upon the side plane of the pad oxide layer under the nitride layer serving as the mask during selective oxidation of the silicon substrate, thereby creating what is called a bird's beak at the end portion of the field oxide layer. Due to the bird's beak, the field oxide layer extends into the active region of the memory cell thereby decreasing the width of the active region. This phenomenon is undesirable because it degrades the electrical characteristics of the memory device.
For this reason, a shallow trench isolation (hereinafter referred to as “STI”) structure is used in making ultra-high scale semiconductor devices. In the STI process, a silicon substrate is first etched to form a trench, and then an oxide layer is deposited to fill up the trench. Thereafter, the oxide layer is etched via an etch back or a chemical mechanical polishing (CMP) method so as to form a field oxide layer inside the trench.
The foregoing LOCOS and STI methods commonly include a mask step that defines the regions of the isolation structure on the substrate and a step that forms the field oxide layer within those regions. After forming the isolation structure, steps to form the memory cells are carried out. As such, alignment errors associated with forming the isolation structure and memory cells aggregate to induce mis-alignment, which may result in failure of the device.
When making a floating gate of a non-volatile memory device, for example, one method of reducing misalignment includes forming STI structure using a self-aligned floating gate, such as by the process disclosed in U.S. Pat. No. 6,013,551 (issued to Jong Chen, et al). According to the method described therein, a floating gate and active region thereof are simultaneously defined and fabricated using a single mask so that alignment errors do not aggregate.
Non-volatile memory devices have long-time storage capacity, e.g., almost indefinitely. In recent years, demand for such electrically erasable programmable read-only memory devices (EEPROMS) or flash EEPROMS has increased. Memory cells of these devices generally have a vertically stacked gate structure comprising a floating gate formed on the silicon substrate with a tunnel oxide layer interposed therebetween, and a control gate formed over and/or around the floating gate with a dielectric (or insulating) interlayer interposed therebetween. In a flash memory cell having this structure, data is stored by transferring electrons to and from the floating gate, which is achieved by applying a controlled voltage to the control gate and substrate. The dielectric interlayer functions to maintain the potential on the floating gate.
FIGS. 1A
to
1
E are perspective views of a substrate illustrating in succession a method of manufacturing a conventional flash memory device using a self-aligned STI technique. Referring to
FIG. 1A
, after forming an oxide layer
11
on a silicon substrate
10
, a first polysilicon layer
13
and a nitride layer
15
are successively formed on the gate oxide layer
11
. The oxide layer
11
serves as a tunnel oxide layer, i.e., a gate oxide layer, of the flash memory cell. The first polysilicon layer
13
serves as a floating gate. The nitride layer
15
serves as a polish-stopping layer during a subsequent chemical mechanical polishing process.
Referring to
FIG. 1B
, a photolithography process is performed to pattern the nitride layer
15
, the first polysilicon layer
13
, and the oxide layer
11
to form a nitride layer pattern
16
, a first polysilicon layer pattern
14
, and an oxide layer pattern
12
. Thereafter, exposed portions of the substrate
10
are etched to a predetermined depth to form trenches
18
. That is, the active regions and floating gates are simultaneously defined during the trench forming process using a single mask.
Referring to
FIG. 1C
, exposed portions of trenches
18
are subjected to thermal treatment in an oxygen atmosphere for curing silicon damages caused by high-energy ion bombardment during the trench etching process. By doing so, a trench inner-wall oxide layer
20
is formed along the inner surface including the bottom plane and sidewall of the trenches
18
by the oxidation reaction of the exposed silicon with an oxidant.
As widely known in the art, a reaction for forming an oxide layer is written as below:
Si+O
2
, H
2
O→SiO
2
As noted from the above reaction, since the diffusion of oxygen into the layer having the silicon (Si) source effects oxidation of silicon, the oxidation reaction occurs at the interface between the first polysilicon layer pattern
14
and the oxide layer pattern
12
, and at the interface between the oxide layer pattern
12
and the silicon substrate
10
. On the contrary, since the amount of silicon in the edge portions of the first polysilicon layer pattern
14
is smaller than that in the other portions, an oxide layer is less grown on the edge portions than on the plane portions.
Therefore, the volume expansion due to the oxidation is limited on the edges of the interface between the first polysilicon layer pattern
14
and the oxide layer pattern
12
and the interface between the oxide layer pattern
12
and the silicon substrate
10
. Since the stress due to the volume expansion is concentrated on these interface edges, the diffusion of oxygen progresses slowly to suppress the oxidation. As a result, because bottom edge portions of the first polysilicon layer pattern
14
are bent outward as shown in
FIG. 2
, the sidewalls of the first polysilicon layer pattern
14
have positive slope. Here, the positive slope denotes that the slope allows the sidewall erosion with respect to the etchant. In other words, as shown in the drawing, the intrusion of the oxidant into the portion underlying the nitride layer pattern
16
is blocked by the existence of nitride laye

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