Method for self-aligned doubled patterning lithography

Details Method for self-aligned doubled patterning lithography Method for self-aligned doubled patterning lithography

2008-11-04

2010-12-21

Kik, Phallaka (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C430S005000, C378S035000, C700S120000, C700S121000

Reexamination Certificate

active

07856613

ABSTRACT:
Various embodiments of the invention provide systems and methods for semiconductor device fabrication and generation of photomasks for patterning a target layout of line features and large features. Embodiments of the invention are directed towards systems and methods using self-aligned double pattern to define the target layout of line features and large features.

REFERENCES:
patent: 7174520 (2007-02-01), White et al.
patent: 2008/0216027 (2008-09-01), White et al.
patent: 2009/0031261 (2009-01-01), Smith et al.

Affiliated with

Also associated with

Rating

Method for self-aligned doubled patterning lithography does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for self-aligned doubled patterning lithography, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for self-aligned doubled patterning lithography will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4209939