Semiconductor device manufacturing: process – Introduction of conductivity modifying dopant into... – Diffusing a dopant
Reexamination Certificate
2000-07-27
2002-12-24
Gulakowski, Randy (Department: 1746)
Semiconductor device manufacturing: process
Introduction of conductivity modifying dopant into...
Diffusing a dopant
C438S751000, C438S756000, C438S757000, C438S559000, C438S563000, C438S569000, C438S914000, C438S923000, C438S924000, C438S970000, C438S976000, C438S705000, C216S097000, C216S099000
Reexamination Certificate
active
06498079
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to semiconductor processes and devices and more specifically to a method for forming a highly doped and/or deep profile doped region and the resulting devices formed therefrom.
BACKGROUND OF THE INVENTION
A Several methods are known for forming deep profile and/or highly doped impurity regions. Ion implanters are frequently used to drive impurities into a semiconductor substrate to formed doped regions, as is well known in the art. Such machines cost several millions of dollars each and it would be impractical to use an ion implanter to drive impurities deep into the substrate because of the amount of processing time that would be required. In this context a deep profile is roughly five microns or more. Likewise, for a very high concentration impurity region in the range of around 10
18
atoms/cm
3
or more, the time required for processing using an ion implanter would be prohibitively expensive.
As an alternative to ion implanting, some in the art have deposited an impurity containing layer on the surface of the semiconductor substrate (or to selected regions of the substrate) and have diffused the desired impurity into the substrate from the impurity containing layer. One example is the use of a boron silicon glass (BSG) layer being placed on the substrate surface in order to form a highly doped boron region in the substrate.
FIG. 1
illustrates a prior art method for forming a highly doped, deep profile boron region using a BSG layer. Substrate
1
had formed on its major surface an oxide layer
3
over which is formed a masking silicon nitride layer
5
. Oxide layer
3
is formed between substrate
1
and nitride layer
5
to minimize stress arising from thermal expansion mismatch between the silicon substrate
1
and the nitride layer
5
.
As shown, masking nitride layer
5
and oxide layer
3
have been patterned to form an opening
9
to expose substrate
1
. After patterning, boron silicon glass (BSG) layer
7
is formed over the device, overlying silicon masking layer
5
and contacting the surface of substrate
1
in the opening
9
. The BSG layer
7
acts as boron source for a subsequent diffusion step. The device is subject to a diffusion step at high temperature (typically 1100-1200 C.) in a nitrogen environment, during which boron migrates from the BSG layer
7
and diffuses into substrate
1
, resulting in doped region
11
within the substrate. A thin film of boron silicon nitride
13
is also formed during the diffusion step. This boron silicon nitride is an undesirable consequence of the diffusion step and must be removed prior to further processing.
After diffusion, BSG layer
7
is removed, typically using hydrofluoric (HF) etch. While the HF etch provides desirable properties for removing BSG layer
7
, it is not effective at removing the undesirable boron silicon nitride layer
13
. Phosphoric acid is used to remove the nitride masking layer
5
as well as to remove the formed boron silicon nitride layer
13
. The phosphoric acid exhibits low selectivity to and undesirably etches the silicon substrate as well—this causes damage to the silicon substrate and can have adverse consequences on the electronic devices to be subsequently formed in the silicon substrate.
Therefore, a need exists in the prior art for a method of forming highly doped and/or deep profile impurity regions which is not prohibitively expensive and which does not damage the silicon substrate. The method should also be compatible with conventional processing methods and techniques.
SUMMARY OF THE INVENTION
In one aspect, the present invention provides a method of forming an impurity region in a substrate. The method includes forming an etch stop layer on a surface of the substrate, forming a sacrificial layer on the etch stop layer, and forming a masking layer on the sacrificial layer. The masking layer is patterned to form an opening exposing a region of the sacrificial layer. An impurity source layer is then formed on the masking layer and the exposed region of the sacrificial layer, and an impurity from the impurity source layer is diffuses through the sacrificial layer and etch stop layer and into the substrate, whereby the sacrificial layer traps undesirable impurities.
In another aspect, the invention provides a method of forming doped region in a silicon substrate. The method comprises forming an oxide layer on the substrate, forming a polysilicon layer on the oxide layer, forming a nitride layer on the polysilicon layer, and patterning the nitride layer to form openings to the underlying polysilicon layer. The method further comprises providing an impurity source in proximity to the wafer, and diffusing impurities from the impurity source through the polysilicon layer and the oxide layer into the substrate. Additionally, the method includes removing the nitride layer, removing the polysilicon layer, whereby the oxide layer acts as an etch stop, and removing the oxide layer.
REFERENCES:
patent: 4669176 (1987-06-01), Kato
patent: 4676847 (1987-06-01), Lin
patent: 4693781 (1987-09-01), Leung et al.
patent: 5273934 (1993-12-01), Ehinger et al.
patent: 5324684 (1994-06-01), Kermani et al.
patent: 5913132 (1999-06-01), Tsai
patent: 5985728 (1999-11-01), Jennings
patent: 6184050 (2001-02-01), Hsu
Bryant Frank Randolph
Smiley Kenneth Wayne
Gulakowski Randy
Slater Steven H.
Smetana J
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