Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
1999-01-04
2001-02-20
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S682000, C438S664000, C438S655000, C438S651000, C438S299000, C438S301000
Reexamination Certificate
active
06191018
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to processes for the manufacture of semiconductor devices and more particularly to processes for forming polycide conductive wiring and polycide gate electrodes for polysilicon gate field effect transistor integrated circuits.
(2) Background of the invention and description of prior art
Refractory metals and their silicides have found widespread use in the manufacture of very large scale integrated circuits. Tungsten silicide(WSi
2
) is frequently selectively formed over exposed silicon surfaces by depositing a tungsten layer, annealing to react the layer with the silicon areas and etching away the unreacted tungsten, leaving tungsten silicide only on the silicon. Other refractory metal silicides, for example MoSi
2
, TaSi
2
, TiSi
2
, and CoSi
2
have also been formed over polysilicon lines, gate electrodes, and interconnects to form the composite polysilicon/silicide layers which are referred to in the art as polycide layers. The metal silicide portion of the polycide layer greatly enhances the conductivity of the polycide conductor and thereby improving device performance.
The most widely used and best understood metal suicides are TiSi
2
and WSi
2
. TiSi
2
is generally formed by deposition of the Ti onto the polysilicon and then annealing at a temperature around 600° C. or less to form the silicide. Next, after removing unreacted Ti, a second, higher temperature, anneal is performed to convert the C49 crystalline phase of TiSi
2
to the higher conductivity C54 crystalline phase. Apte, et.al., U.S. Pat. No. 5,593,924 shows that amorphization of the silicon surface by ion implantation before silicide formation. A capping layer of TiN applied over the silicide prevents contamination. This is believed to increase the percentage of C49 phase which transforms to C54 phase during a subsequent anneal, thereby reducing the resistivity and improving the uniformity of the polycide.
Refractory metal suicides may also be formed by depositing the metal suicide onto a polysilicon layer prior to patterning. Chang, C. Y. and Sze, S. M., “ULSI Technology” McGraw-Hill, N.Y., (1996), p 393-4 shows several methods for forming metal silicides by reactions of refractory metal precursors with silane and dichlorosilane. Price, U.S. Pat. No. 4,692,343 cites the formation of tungsten suicide by a PECVD (plasma enhanced chemical vapor deposition) process using WF
6
and SiH
2
Cl
2
.
Liu, U.S. Pat. No. 5,514,617 cites ion implantation of polysilicon or polycide layers with conventional semiconductor dopants such as arsenic, boron, phosphorous, and BF
2
+
ions to form load resistors in poly-load SRAM(static random access memory) integrated circuits.
Fujii, et. al. in U.S. Pat. No. 5,355,010 shows a method for forming a silicide layer over a polysilicon layer which has—and p-type regions. The silicide layer is ion implanted with the p-type impurity boron, in order to have a substantially uniform concentration in the silicide layer thereby preventing out-diffusion from the polysilicon layer. NeppI, et. al., U.S. Pat. No. 4,640,844 shows ion implantation of dopants into the metal silicide layer of polycide gate electrodes. The dopants are thereafter diffused into the subjacent polysilicon.
Generally, the resistivity of the polycide layers is controlled by the deposition parameters and a high temperature annealing step. Blanket ion implantation has been applied to amorphise the polysilicon prior to forming the silicide layer. Amorphization of the polysilicon facilitates the transition of the higher resistivity C49 crystalline phase of the silicide to the lower resistivity C54 phase. Resistivity modification of polysilicon is made possible by incorporation of semiconductive dopant impurities, either by ion implantation or by in-situ doping during deposition, because of the semiconductive property of polysilicon. Metal suicides such as tungsten silicide do not behave as semiconductors, and are applied over polysilicon layers to lower the overall resistance of the resultant polycide layer as much as possible.
None of the known prior art seeks to controllably modify the resistivity of the metal silicide portion of the polycide layer in order to achieve a particular value of resistivity which is stable over the remainder of the chip processing. The circuit designer is thereby left with a polycide layer of a single, usually low as possible, resistivity from which to fabricate various and sundry resistive components, interconnects, gate electrodes, and long polycide wiring runs directed by the circuit design. He thus must size the all the components which are to be formed in a polycide layer of a single resistivity. Resistors formed from the polycide layer must then be made with relatively large areas if the polycide layer is to provide high conductivity for long wiring runs and interconnects. Component requiring large RC time constants must be accommodated by greater area consumption. Surface area, often referred to as “real estate” is at a premium in high density integrated circuits and must be used as efficiently as possible. It would therefore be of great advantage to design integrated circuits with more than one choice of polycide resistivity. This would add an additional degree of freedom at this level which would permit high performance as well reduced real estate usage.
It would therefore be desirable to have a means for selectively adjusting the resistivity of portions of the silicide layer wherein a higher resistivity is available to circuit designers.
SUMMARY OF THE INVENTION
It is an object of this invention to provide a method for adjusting the resistivity of suicide films to a predetermined value.
It is another object of this invention to provide a method for stabilizing the resistivity of a suicide film after adjustment so that the resistivity is not affected during subsequent processing.
It is another object of this invention to provide a method for providing a polycide layers having regions with different resisitivities whereby circuit designers may select optimal resistivities for high and low resistivity components. Such regions may be used to form integrated circuit components such as resistors, delay lines, and other resistive elements.
It is yet another object of this invention to provide a method for improving the efficiency of space utilization of high density integrated circuit components without compromising circuit performance.
These and other objects which will become apparent are accomplished by masking an integrated circuit wafer after formation of the refractory metal silicide to expose selected regions. Impurity ions are then implanted into the exposed metal silicide. The implanted ions modify the resistivity of the metal silicide in the selected regions. After implantation, the mask is removed and the wafer is subjected to a high temperature anneal which forms a low resistivity polycide in the masked regions and a higher resistivity polycide in the selected regions which received the ion implantation. The high temperature anneal, which is preferably by RTA (rapid thermal annealing) stabilizes the resistivity of the metal silicide in that subsequent exposure of the metal silicide to ion implantation does not alter it's resistivity.
REFERENCES:
patent: 4640844 (1987-02-01), Neppl et al.
patent: 4692343 (1987-09-01), Price et al.
patent: 5355010 (1994-10-01), Fujii et al.
patent: 5356826 (1994-10-01), Natsume
patent: 5397729 (1995-03-01), Kayanuma et al.
patent: 5413957 (1995-05-01), Byun
patent: 5514617 (1996-05-01), Liu
patent: 5593924 (1997-01-01), Apte et al.
patent: 5631188 (1997-05-01), Chang et al.
patent: 5937325 (1999-08-01), Ishida
patent: 5960319 (1999-09-01), Iwata et al.
patent: 5965617 (1999-09-01), Kimura et al.
patent: 5989996 (1999-11-01), Kishi
patent: 6030863 (2000-02-01), Chang et al.
patent: 6034401 (2000-03-01), Hsia et al.
Chang et al., “ULSI Technology”, The McGraw-Hill Companies, 1996, pp. 393-396.
Chang Tzong-Sheng
Tsao Hsun-Chih
Yue Wen-Jye
Ackerman Stephen B.
Bowers Charles
Nguyen Thanh
Saile George O.
Taiwan Semiconductor Manufacturing Company
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