Method for selective oxide etching in pre-metal deposition

Details Method for selective oxide etching in pre-metal deposition Method for selective oxide etching in pre-metal deposition

1999-11-19

2003-03-11

Goudreau, George (Department: 1763)

Cleaning and liquid contact with solids

Processes

Including application of electrical radiant or wave energy...

C134S001300, C438S723000, C438S719000, C438S734000, C438S704000, C438S706000, C438S750000, C438S756000

Reexamination Certificate

active

06530380

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to the field of microelectronics fabrication. More particularly, the invention relates to the removal of dielectric material during fabrication of closely spaced structures employed in microelectronics fabrications.
2. Description of the Related Art
Microelectronics fabrications employ layers of microelectronics materials formed over substrates and patterned to embody the active devices and other components which are interconnected to form the circuitry of microelectronics fabrications. The formation of low resistance electrical contacts is an important factor in achieving the desired circuit performance in such microelectronics fabrications. Increased density of components employed within microelectronics fabrications has resulted in closer spacing between the structures which constitute the components such as low resistance electrical contacts among others.
Electrical contacts may be formed employing metal silicide compound conductor materials which have low electrical resistance. When such silicide materials are employed in microelectronics fabrications in such a fashion as to form self-aligned suicide and contact regions, such contacts are commonly referred to as salicide (self-aligned silicide) contacts. Self alignment of the salicide contact may be achieved, for example, by etching through a dielectric layer to form contact regions in an underlying silicon conductor layer. After deposition of the appropriate metal layer, a treatment such as rapid thermal heating brings about formation of the metal silicide compound layer in the contact regions only, with the superfluous metal being removed. Adjacent to salicide contact layers commonly are formed dielectric spacer layers.
Salicide contacts and contact layers have become increasingly widely employed in microelectronics fabrications. The self-aligning feature and inherently low electrical resistance of the silicide materials are especially important as dimensions and ground rules have diminished. The formation of salicide contacts is not without problems, however.
For example, the unmasked dielectric layer which is adjacent to the masked salicide block etch layer prior to selective salicidation of the microelectronics fabrication must be subsequently removed prior to further processing. Customarily, silicon oxide layers are employed as salicide block etch layers. The subsequent removal of silicon oxide by chemical etching, particularly in narrow gaps, may result in damage to other silicon oxide layers, in particular gap filling silicon oxide layers in shallow isolation trenches, field oxide isolation layers and the like.
It is thus towards the goal of improved methods for removing dielectric material employed within microelectronics fabrications with closely spaced features such as employed for salicide electrical contact formation that the present invention is generally directed.
Various methods have been disclosed for employing and removing dielectric layers employed in forming salicide contacts within microelectronics fabrications.
For example, Yoo, in U.S. Pat. No. 5,573,980, discloses a method for forming self aligned silicide contacts in a silicon integrated circuit without stringers or stray silicide conductor paths. The method employs a thin polysilicon layer patterned so as to cover only the contact region desired. A metal layer such as titanium is then deposited over the silicon and the titanium silicide contact layer formed, the excess titanium then being etched away.
Further, Naem, in U.S. Pat. No. 5,780,349, discloses a method for forming self-aligned gate, source and drain cobalt silicide contacts to MOSFET devices. The method employs ion implantation of a dopant into the patterned polysilicon layer first formed over the gate, source and drain electrode areas, followed by thermal annealing to disperse and activate the dopant. Then a layer of cobalt is formed over the patterned polysilicon layer and a second ion implantation with heavy ions employed to mix the cobalt and silicon materials at their interface. A second rapid thermal annealing is then employed to form the cobalt silicide salicide contacts.
Still further, Huang, in U.S. Pat. No. 5,863,820, discloses a method for forming contacts to memory and logic circuits on the same chip, employing salicide contacts for the logic circuits and SAC contacts to the memory circuits. The method employs a protective coating of silicon oxide to mask the memory device portion of the chip so that the salicide contacts may be formed on the logic device portion of the chip. Then, while the logic device portion is protected, the memory device portion is provided with self-aligned contacts (SAC).
Finally, Pan et al., in U.S. Pat. No. 5,869,396, disclose a method for forming a self-aligned polycide gate electrode within a field effect transistor (FET) wherein the metal silicide portion of the gate electrode does not encroach upon adjacent device areas. The method employs a patterned polysilicon layer whose surface is exposed by planarizing an overlying blanket insulator layer. The exposed patterned polysilicon layer is then covered with a patterned metal silicide layer, so as to form a polycide gate electrode.
Desirable in the art of microelectronics fabrication are additional methods for forming and removing dielectric layers employed in forming salicide contacts selectively and with attenuated degradative effects.
It is towards these goals that the present invention is generally and more specifically directed.
SUMMARY OF THE INVENTION
It is a first object of the present invention to provide a method for complete removal of dielectric layers from selected regions of substrates employed within microelectronics fabrications.
It is a second object of the present invention to provide a method in accord with the first object of the present invention, where the unmasked dielectric layer outside the salicide block etch layer is readily removed selectively between closely spaced structures with attenuated degradation of the microelectronics fabrication.
It is a third object of the present invention to provide a method in accord with the first method of the present invention and/or the second object of the present invention, where the method is readily commercially implemented.
In accord with the goals of the present invention, there is provided a method for removing completely dielectric layers formed upon a substrate employed within a microelectronics fabrication from regions wherein closely spaced structures such as self-aligned silicide or salicide electrical contacts have been fabricated, with attenuated degradation of the microelectronics fabrication. To practice the invention, there are first provided closely spaced structures within a substrate employed within a microelectronics fabrication. There is formed over the substrate a salicide block layer employing silicon containing glass dielectric material which may be selectively doped. There is then formed a patterned photoresist etch mask layer over the substrate. Employing the patterned photoresist etch mask layer, there is then etched the pattern of the desired salicide contact region through the salicide block layer to remove completely silicon containing dielectric block layer without degrading other features of the substrate surface, in particular the silicon oxide dielectric material formed within the shallow trench isolation layer.
The present invention may be employed to form selective regions for salicide contact fabrication on silicon substrates or silicon layers formed upon substrates employed within microelectronics fabrications including but not limited to integrated circuit microelectronics fabrications, solar cell microelectronics fabrications, charge coupled device microelectrorics fabrications, ceramic substrate microelectronics fabrications and flat panel display microelectronics fabrications.
The present invention employs methods and materials which are known in the art of microelectronics fabrication, but arranged in a novel order

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