Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Patent
1996-11-20
1998-09-15
Bowers, Jr., Charles L.
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
438655, 438656, H01L 2144
Patent
active
058077880
ABSTRACT:
A method and the device produced by the method of selective refractory metal growth/deposition on exposed silicon, but not on the field oxide is disclosed. The method includes preconditioning a wafer in a DHF dip followed by the steps of 1) selectively depositing a refractory metal on the exposed surfaces of the silicon substrate by reacting a refractory metal halide with the exposed surfaces of said silicon substrate; 2) limiting silicon substrate consumption by reacting the refractory metal halide with a silicon containing gas; and 3) further increasing the refractory metal thickness by reacting the refractory metal halide with hydrogen. Through an adequate pretreatment and selection of the parameters of 1) temperature; 2) pressure; 3) time; 4) flow and 5) flow ratio during each of the deposition steps, this invention adequately addresses the difficulties of uneven n+ versus p+ (source/drain) growth, deep consumption/encroachment by the refractory metal into silicon regions (e.g., worm holes), poor adhesion, uncontrolled selectivity and uneven morphology.
REFERENCES:
patent: 4740483 (1988-04-01), Tobin
patent: 5084417 (1992-01-01), Joshi et al.
patent: 5112439 (1992-05-01), Reisman et al.
patent: 5202287 (1993-04-01), Joshi et al.
patent: 5221853 (1993-06-01), Joshi et al.
patent: 5433975 (1995-07-01), Roberts et al.
D. Hisamoto, et al., "Metallized Ultra-Shallow-Junction Device Technology for . . . " IEEE Transactions on Electron Devices, vol. 41, No. 5, May 1994, pp. 745-750.
Y. Nakamura, et al., "Surface Reaction Controlled W-CVD Technology for 0.1um . . . ".
T. Kosugi, et al., "Novel Si Surface Cleaning Technology with Plasma Hydrogenation and Its . . . ", 1995 Symposium on VLSI Technology Digest of Technical Papers, pp. 41-42.
M. Sekine, et al., "Self-Aligned Tungsten Strapped Source/Drain and Gate Technology . . . ", IEEE, International Electron Devices Meeting 1994, Technical Digest, pp. 19.3.1-19.3.4.
Y. Nakamura, et al., "Mechanism Causing p+
+ Growth Differences and Encroachment in Selective W-stacked CMOS Applications", Semiconductor Development Center, Semiconductor & Integrated Circuits Div., Hitachi, Ltd., pp. 1-6.
D. Hisamoto, et al., "High-Performance Sub-0.1-um CMOS with Low-Resistance T-Shaped Gated Fabricated by Selective CVD-W", 1995 Symposium on VLSI Technology, Digest of Technical Papers, IEEE, pp. 115-116.
Brodsky Stephen Bruce
Conti Richard Anthony
Subbanna Seshadri
Abate, Esq. Joseph P.
Berry Renee R.
Bowers Jr. Charles L.
International Business Machines - Corporation
LandOfFree
Method for selective deposition of refractory metal and device f does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for selective deposition of refractory metal and device f, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for selective deposition of refractory metal and device f will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-86639