Method for selecting optimal I/O buffer

Details Method for selecting optimal I/O buffer Method for selecting optimal I/O buffer

2006-01-31

2006-01-31

Tan, Vibol (Department: 2819)

Electronic digital logic circuitry

Interface

Current driving

C326S021000, C326S029000, C327S108000

Reexamination Certificate

active

06992507

ABSTRACT:
A method for selecting an I/O buffer. The method includes providing a plurality of I/O buffers. Each one of the plurality of I/O buffers has a different performance characteristic. Each one of the plurality of I/O buffers is coupled to a receiving device through a corresponding one of a plurality of transmission lines. Each one of the plurality of buffers is driven by a logic signal. Each one of the transmission lines produces a corresponding series of output logic signals. The plurality of output signals is observed. The method includes selecting one of the plurality of I/O buffers in accordance with the observed output signals.

REFERENCES:
patent: 6414525 (2002-07-01), Urakawa
patent: 6486696 (2002-11-01), Cao
patent: 2003/0204765 (2003-10-01), Hall
patent: 2004/0170066 (2004-09-01), Gallo et al.
“RapidIO Interconnect Specification:” Rev. 1.2/2002 Appendix A pp. IV-109 through IV-115.

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