Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1998-04-28
2001-06-05
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06243854
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to systems for processing very large scale integration (VLSI) physical designs. More particularly, it relates to a method for increasing access and control over hierarchical information in a shape processing system used in VLSI.
2. Prior Art
Current systems for processing VLSI physical designs exploit the nested, hierarchical structure of such designs to reduce the time and storage requirements for shape processing operations. Although the details of the hierarchical processing are usually not disclosed to the user, it is occasionally desirable to provide access to and control over the handling of a design's hierarchical structure. Such access and control provides the user with the ability to optimize performance of the shape-processing application.
With the shape processing systems of the prior art, the degree of hierarchical access and control are generally limited. Examples of such systems are the NIAGARA Extensible Shapes Processor and the Avanti! (formerly ISS) Hercules™. The NIAGARA system provides two modes for hierarchical processing, (1) cellwise mode, and (2) Full mode. In cellwise mode, the shapes of each cell of a hierarchical design are considered in isolation, and the possible interaction with shapes in other cells are ignored. In the Full mode, all possible shape interactions are considered.
The advantage to processing in cellwise mode is that it can potentially reduce storage and execution times by effectively partitioning the design into subdesigns (one per cell), processing the subdesigns independently, and then combining the results. The ability to select cellwise vs. full mode can be provided to the application programmer in several ways. For example, a global specification (e.g., via a command-line argument) can be used to indicate that all operations in a particular run of a shape-processing application are to be performed in either cellwise or full mode. In another example, a statement-by-statement specification can be used to indicate that particular operations are to be performed in one or the other of the two modes.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to extend the degree of access and control over hierarchical information in a hierarchical shape processing system.
It is another object of the invention to provide a method for hierarchical shape processing that performs more efficiently than existing methods.
It is yet another object of the invention to provide a method for hierarchical shape processing that can be used for design verification and design modification that enhances the manufacturability of the physical design.
These and other objects of the invention are achieved by providing the application programmer with additional or an extended set of modes for hierarchical processing. According to an embodiment of the present invention, shape information including relationships between each cell containing the shapes and every other cell in the hierarchical design are received and input into a processing system. Hierarchical relationships between the shapes are specified to constrain the identification of pairs. Each pair of shapes that satisfy the constraint (hierarchical relationship) are identified. Subsequently, all shapes that are considered pairs with a particular shape in view of the constraint are also identified. These shapes are called “neighbors”. Once these neighbors are identified, a shape processing function (e.g., shape transformation, measurement, predicate, etc.) is applied to the particular shape and its neighbors, and the result is outputted.
The constraints placed on the shape processing can be varied to extend the hierarchical interaction selection depending on a desired shape processing mode. Examples of such constraints are “childcell”, “parentcell”, “samecell”, and “peercell”.
The extended hierarchical interaction selection approach and mechanisms of the present invention can be adapted to any system that processes hierarchical physical designs for purposes of design verification and/or design modification. Examples of such systems are the Avant!, Inc. Hercules™, Cadence Dracula™, Diva™, Vampire™, and Mentor Graphics Calibre™.
These systems generally all provide the “cellwise mode” described above, but do not provide the extended hierarchical interaction selection of the present invention. It is possible to use selective cell “flattening” and “exploding” capabilities of these systems in an attempt to achieve similar storage and execution efficiencies of the extended modes of the present invention. However, these capabilities have undesirable effects of themselves incurring storage and execution time overheads, and in addition, introducing undesirable changes in a design's hierarchical structure, which may compromise subsequent operations.
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Kim Young O.
Lavin Mark A.
Pokorny William F.
Sayah Robert T.
F. Chau & Associates LLP
International Business Machines - Corporation
Siek Vuthe
Smith Matthew
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