Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure
Reexamination Certificate
2000-10-02
2004-11-09
Lee, Hsien Ming (Department: 2823)
Active solid-state devices (e.g., transistors, solid-state diode
Test or calibration structure
C257S686000, C438S014000, C438S015000, C438S106000, C438S107000
Reexamination Certificate
active
06815712
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention relates in general to integrated circuits and, more particularly, to wafer level testing of chips from a wafer that is coupled to an interposer for the selection of components for a matched set.
BACKGROUND OF THE INVENTION
Modern electronic devices utilize semiconductor chips, commonly referred to as integrated circuits, which incorporate numerous electronic elements. These chips are mounted on substrates which physically support the chips and electrically interconnect the chips with other elements of the circuit. Such substrates may then be secured to an external circuit board or chassis.
The size of the chips and substrate assembly is a major concern in modern electronic product design. The size of each subassembly influences the size of the overall electronic device. Moreover, the size of each subassembly controls the required distance between each chip and between chips and other elements of the circuit. Delays in transmission of electrical signals between chips are directly related to these distances. These delays limit the speed of operation of the device. Thus, more compact interconnection assemblies, with smaller distances between chips and smaller signal transmission delays, can permit faster operations.
One approach for improving overall system performance is through the use of matched sets. For example, several identical or dissimilar components that have been identified by the individual testing phase of component processing to have certain performance tracking characteristics may be assembled together as a matched set. The components of such a matched sets are frequently attached to a single substrate in close proximity to one another. This strategy improves performance compared to conventional or non-optimized systems by reducing the overall space needed to accommodate the chips and by, among other things, shortening the distance between chips. Specifically, interconnect inductance and signal transmission delays are all reduced.
One type of matched set includes a collection of identical components which have been identified to meet specific system performance requirements. For example, radio frequency (RF) systems often employ identical filters, switches, power dividers, mixers and high frequency amplifiers. Typically, each of the identical components has been extensively tested individually prior to inclusion in this type of system. The individual characterization tests for a filter, for instance, might measure insertion loss and phase shift as a function of frequency, input power and temperature. These multi-dimensional arrays of data are then compared to each other to identify individual components that perform within acceptable limits relative to each other. Components that are found to exhibit similar behavior under the various input stimuli will constitute a matched set of identical devices. Conversely, components that are found to exhibit dissimilar behavior under the various input stimuli, for example, the gain of one component having a negative slope over temperature while the gain of another component having a positive slope over temperature, will constitute a mismatch of components that will not be placed in a chip collection.
It has been found, however, the certain mismatches are not identified when the components are tested individually. In fact, certain mismatches are not identified until the entire chip collection is assembled and the components are tested together for the first time. As such, some chip collections must be disassembled so that the valuable components may be, for example, packaged as individual components, while other chip collections are simple discarded.
Therefore, a need has arisen for an improved method for selection of system components for a matched set. A need has also arisen for such a method that does not require elaborate data reduction of test results from individually tested components. Additionally, a need has arisen for such a method that allows for testing of the individual components together prior to the assembly of the matched set.
SUMMARY OF THE INVENTION
The present invention disclosed herein provides a chip collection, known as a matched set, that maximizes system performance by selecting well matched integrated circuit chips for assembly together into the matched set. The present invention achieves this result by allowing for testing of the various integrated circuit chips together prior to the assembly of the matched set. This testing is performed by connecting a wafer level interposer and a wafer to a testing apparatus. Thus, all of the chips to be included in the matched set may be tested together. After testing, the wafer-interposer assembly is diced into a plurality of chip assemblies that are assembled into the matched set.
In its broadest form, the present invention provides for the attachment of a semiconductor wafer having a plurality of integrated circuit chips thereon to an interposer for testing of the integrated circuit chips. The integrated circuit chips of the wafer may be, for example, DRAM chips, SRAM chips, amplifiers, controllers, converters or other devices that are commonly assembled in sets. Likewise, the integrated circuit chips of the wafer may be designed to carry any type of signal such as an analog signals, a digital signal, an RF signal or a mixed signal and the like.
Prior to testing, the wafer is electrically and mechanically coupling to the interposer such that the wafer-interposer assembly may be connected to a testing apparatus. The testing may include performance tests over a range of temperatures, including burn-in testing, vibration testing, testing for leakage currents, testing for offset voltages, testing for gain tracking, testing for bandwidth and the like to determine which integrated circuit chips from the wafer could be included in a matched set with other integrated circuit chips from that wafer to achieve optimum performance. Likewise, the testing may include grading of the integrated circuit chips for speed or other performance characteristics such that the integrated circuit chips that receive a particular grade are matched with other integrated circuit chips from that wafer having a similar grade. Additionally, the testing may include testing for non-conformance wherein certain integrated circuit chips may not be matched with any other integrated circuit chips from that wafer.
Once testing is complete, the wafer-interposer assembly may be diced into a plurality of chip assemblies. Two or more of these chip assemblies may them be matched with one another, for inclusion in a matched set. This selection is based upon the results of the testing of the integrated circuit chips. Using this process, all or substantially all of the integrated circuit chips from the wafer may be matched with other integrated circuit chips from that wafer based upon the desired performance characteristics of the matched set that will contain these devices. By performing the testing prior to assembly of the matched set, the performance characteristics of each of the matched sets assembled using integrated circuit chips from the tested wafer is enhanced as is the overall performance of the entire lot of matched set devices.
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Danamraj & Youst P.C.
Eaglestone Partners I, LLC
Lee Hsien Ming
Youst Lawrence R.
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