Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-09-08
2009-11-10
Lin, Sun J (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
07617477
ABSTRACT:
Methods are disclosed for selecting and optimizing an exposure tool using an individual mask error model. In one embodiment, a method includes selecting a model of a lithography process including an optical model of an exposure tool and a resist model, creating an individual mask error model representing a mask manufactured using mask layout data, simulating the lithography process using the model of the lithography process and the individual mask error model to produce simulated patterns, determining differences between the simulated patterns and a design target, and optimizing settings of the exposure tool based on the differences between the simulated patterns and the design target.
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Hunsche Stefan
Ye Jun
Brion Technologies, Inc.
Lin Sun J
Pillsbury Winthrop Shaw & Pittman LLP
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