Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Reexamination Certificate
2006-08-29
2006-08-29
Elmore, Reba I. (Department: 2189)
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
C711S154000, C711S165000, C710S068000, C714S764000
Reexamination Certificate
active
07100004
ABSTRACT:
Memory is scrubbed by an improved non-linear method giving scrubbing preference to the central storage region having the characteristic of a high risk read-only memory such as the CPA region to prevent the accumulation of temporary data errors. The chip row on which the CPA resides is scrubbed after each time the scrubbing of a non-CPA chip row in a PMA completed successfully. The next non-CPA least recently scrubbed chip row would be selected for scrubbing after scrubbing completed on the CPA chip row. This in a first case provides non-linear selection methods of scrubbing central storage of computer systems to more frequently select (“select” herein encompasses the meaning of “favor”) scrub regions having the characteristic of a predominately read-only memory making those regions at a higher risk of failure than those regions having lower risk because of frequent write operations. In a second case, scrub regions having the characteristic of a predominately read-only memory are selected by using a second preferred embodiment selection method which uses the detection of faulty data from normal system accesses to central storage to identify other high risk regions and scrub them before other lower risk regions. In addition, the severity of the detected data error can be used to determine the rate at which scrub commands are sent to the selected region: the higher the severity, the higher the scrub rate.
REFERENCES:
patent: 5267242 (1993-11-01), Lavallee et al.
patent: 6446145 (2002-09-01), Har et al.
patent: 6480982 (2002-11-01), Chan et al.
Chen Johnson Judy S.
Kark Kevin W.
Wellwood George C.
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