Method for screening failure of memory cell transistor

Details Method for screening failure of memory cell transistor Method for screening failure of memory cell transistor

2006-02-14

2006-02-14

Hoang, Huan (Department: 2827)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S201000, C365S205000

Reexamination Certificate

active

06999359

ABSTRACT:
The present invention discloses a method for screening a sensing margin generated by a gate residue in a memory cell transistor. The method for screening failure of the memory cell transistor is summarized as follows. A test mode signal for sensing margin control is supplied. A write operation is performed to store data in the cell transistor. A word line is enabled by an active command. Isolated transistors disposed between a bit line coupled to the cell transistor and a bit line coupled to a sense amplifier are disabled to intercept a sensing operation. A voltage of the bit line coupled to the cell transistor is measured for a predetermined time. Here, voltage variations on the bit line are measured to screen failure of the cell transistor.

REFERENCES:
patent: 5373472 (1994-12-01), Ohsawa
patent: 6901014 (2005-05-01), Son et al.

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