Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1999-06-28
2001-12-04
Niebling, John F. (Department: 2812)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06327697
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention provides a method for efficiently routing connections in an integrated circuit which minimizes the length of conductors and minimizes the total amount of metal required to be deposited in order to accomplish the routing.
2. The Background Art
Integrated circuits are complex devices having many different types of functional blocks within them. In situations where similar functions must be performed on many bits of data, circuits performing those functions are duplicated in functional blocks called datapaths. A second type of functional block commonly found in integrated circuits is called a control block. Control blocks typically perform functions relating to directing the flow of data, rather than operating on the data itself.
Integrated circuit designs include not only the individual circuits used in datapaths and control blocks, but also the connectivity between those circuits. The method used to route the conductive paths between various circuits is an important part of integrated circuit layout.
Prior art methods for routing conductive paths in a given area of an integrated circuit typically include three steps. First, the approximate length of each conductive path is determined. Next, all of the conductive paths in the given area are ordered from longest to shortest. Finally, the actual routing of each conductive path is determined, with the longest path being routed first, the next longest being routed second, and each other path being routed in succession from longest to shortest.
Though prior art methods work for their intended purposes, these methods tend to be inefficient in the use of possible vertical and horizontal routing areas, and tend to require more metal lines be deposited than are necessary to accomplish a given routing.
In this disclosure, a “pin” is defined as a contact point on an integrated circuit component where a metal line may be connected.
FIG. 1
is an example of conductive paths routed using prior art methods.
Referring to
FIG. 1
, functional block
10
includes circuitry having a pin
12
which must be connected to pin
14
of block
16
. Correspondingly, pin
18
of block
20
must be connected to pin
22
of block
16
. Finally, pin
24
of block
26
must be routed to pin
28
of block
30
.
Design rules used when routing integrated circuits determine the possible locations for the placement of conductive paths. These locations are commonly called tracks. Horizontal and vertical tracks are typically placed on different metal layers of a multilayer layout.
FIG. 2
shows a typical layout of a prior art functional block.
Referring to
FIG. 2
, functional block
40
includes pins
42
,
44
, and
46
, and tracks
48
a
through
48
o
inclusive.
Two general types of pins are used in integrated circuits: fixed pins and flex pins. Fixed pins are those pins having only a single track leading to them. Pin
46
is an example of a fixed pin. Flex pins are pins which lead to more than one track location. Since the pin is a conductive surface, any track location leading to a given pin may be used in routing. However, prior art methods do not take into account the single or flex nature of a pin. If a pin have multiple choices for tracks to use when making a connection, prior art routers randomly choose one of the multiple available locations.
Referring again to
FIG. 1
, since longer conductive paths are typically routed first, the connection between pins
12
and
14
are routed, followed by pins
24
to
28
, and pins
18
to
22
. It can be seen that pins
12
and
14
have multiple possible track locations. However, in this example, the router has randomly chosen to use a track location which interferes with the ideal location for the conductive path required between fixed pins
18
and
22
. Therefore, the router is forced to route the conductive path between pins
18
and
22
using a track location other than the ideal location, causing the path between pins
18
and
22
to be unnecessarily lengthened, and additional unnecessary metal to be deposited during manufacturing.
It would therefore be beneficial to provide a method for routing conductors which takes into account the types of pins at each end of a given conductive path.
It would also be beneficial to provide a method for routing conductors which minimizes the length of conductive paths and the amount of metal required for required conductive paths.
SUMMARY OF THE INVENTION
A method for routing conductive paths in an integrated circuit, each conductive path having a first pin and a second pin is described herein. The method includes separating at least two conductive paths into groups based on the connection type of each of said conductive paths, the connection type for a given conductive path being determined based on the types of pins at each end of the conductive path, ranking each group based upon how constrained each connection type is relative to each other connection type, choosing the group having the most constrained connection type which has not yet been routed, and routing each conductive path within the group chosen during the choosing operation.
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Niebling John F.
Sierra Patent Group Ltd.
Sun Microsystems Inc.
Whitmore Stacy A
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