Method for resisting an FPGA interface device

Details Method for resisting an FPGA interface device Method for resisting an FPGA interface device

1999-05-14

2002-11-26

Wong, Peter (Department: 2181)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Protocol

C716S030000

Reexamination Certificate

active

06487618

ABSTRACT:

FIELD OF THE INVENTION
This invention relates generally to programmable devices such as field programmable gate arrays (FPGAs), and specifically to methods of resetting FPGA interface devices.
BACKGROUND OF THE INVENTION
FIG. 1
shows a conventional Field Programmable Gate Array (FPGA)
1
having an array of configurable logic blocks (CLBS)
2
surrounded by input/output blocks (IOBs)
3
. The CLBs
2
are individually programmable and can be configured to perform a variety of logic functions ranging from simple AND gates to more complex functions of a few input signals. A programmable interconnect structure
4
includes a matrix of programmable switches (PSMs)
5
which can be programmed to selectively route signals between the various CLBs
2
and IOBs
3
and thus produce more complex functions of many input signals. The IOBs
3
can be configured to drive output signals from the CLBs
2
to external pins (not shown) of FPGA
1
and/or to receive input signals from the external FPGA pins.
The CLBs
2
, IOBs
3
, and PSMs
5
of FPGA
1
are programmed by loading configuration data into memory cells (not shown for simplicity) connected to CLBs
2
, IOBs
3
, and PSMs
5
. These memory cells control various switches and multiplexers within respective CLBs
2
, IOBs
3
, and PSMs
5
which implement logic and routing functions specified by the configuration data in the memory cells. Configuration data is provided to FPGA
1
via a configuration port
6
and thereafter routed to the memory cells using a dedicated configuration structure (not shown here but described in U.S. Pat. Nos. Re34,363, 5,430,687, 5,742,531, and 5,844,829). Configuration port
6
is connected to the dedicated configuration structure by a configuration access port (CAP)
7
, which is essentially a bus access point. Further information regarding various types of FPGAs can be found in “The Programmable Logic Data Book 1998”, published in 1998 by Xilinx, Inc., and available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124.
Configuration data is typically downloaded to an FPGA from a host system such as a personal computer or workstation using an FPGA interface cable, as illustrated in FIG.
2
. Well known design tool software operating on a suitable microprocessor within host system
20
creates a configuration bitstream which embodies the logic functions desired to be implemented by the target FPGA. The configuration bitstream is downloaded from host system
20
to interface cable
15
using, for instance, a serial port or a USB port. The interface cable
15
preferably includes an on-board FPGA that customizes the configuration bitstream received from the host system
20
into a format usable by target FPGA
10
, although in some embodiments host system
20
's microprocessor is used to customize the configuration bitstream for target FPGA
10
. Since an FPGA is able to customize configuration data at a rate much faster than that of a microprocessor, FPGA interface cables having an on-board FPGA provide superior performance.
However, while an FPGA interface cable's on-board FPGA advantageously improves FPGA configuration speeds, configuration speed can be further improved by inclusion of a microcontroller, which by its very presence increases device malfunction risk. For example, an on-board microcontroller will be described that acts as a conduit between the on-board FPGA and host system
20
. If the microcontroller becomes non-responsive to commands from the host system, e.g., the microcontroller executes an endless loop, rendering it frozen, the host system is no longer able to communicate with interface cable
15
, and thus is no longer able to communicate with target FPGA
10
. Without special provisions, the user must manually reset interface cable
15
to regain control of interface cable
15
and target FPGA
10
. Manually resetting interface cable
15
every time its on-board microcontroller becomes non-responsive is time-consuming and inconvenient.
Moreover, where configuration data is downloaded from host system
20
to interface cable
15
via a serial port connection, e.g., an RS-232 serial port, downloading into interface cable
15
's on-board memory via its on-board microcontroller cannot be aborted. When downloading data to interface cable
15
's on-board microcontroller, host system
20
first alerts the on-board microcontroller of the precise size of the download configuration data so that the on-board microcontroller can verify that all configuration data is received. Accordingly, once the download process begins, the on-board microcontroller expects to receive the specified number of data bytes, and therefore interprets the next specified number of bytes as data. Thus, if a command such as, for instance, an “abort download” instruction, were to be sent to interface cable
15
during the configuration data download process, interface cable
15
's on-board microcontroller would interpret the command as data, and therefore ignore the command. Where the download configuration file is large, e.g., several megabytes, waiting for the download to complete before issuing a command is inconvenient.
SUMMARY OF THE INVENTION
The present invention provides a method for communicating with an FPGA interface device having an on-board FPGA and an on-board microcontroller when the on-board microcontroller is not responsive to commands from a host system. In accordance with the present invention, if the host system determines that the microcontroller is not responsive to commands, the host system sends a null character to the interface device at a predetermined baud rate which is significantly distinguishable from baud rates normally used for communicating with the microcontroller. A logic circuit on the interface device monitors the baud rate of incoming data, and if a null character at the predetermined baud rate is detected, the logic circuit toggles the reset pin of the microcontroller. In response thereto, the microcontroller re-boots, and is thereafter able to receive commands from the host system.
Further, in accordance with other embodiments of the present invention, null characters can be sent to the interface device at other predetermined baud rates, also significantly distinguishable from the baud rates normally used, to perform additional functions. In one embodiment, the logic circuit is configured to toggle an interrupt pin of the microcontroller, thereby allowing a download process from the host system to the microcontroller to be aborted.


REFERENCES:
patent: RE34363 (1993-08-01), Freeman
patent: 5430687 (1995-07-01), Hung et al.
patent: 5628028 (1997-05-01), Michelson
patent: 5844829 (1998-12-01), Freidin et al.
patent: 5982837 (1999-11-01), Earnest
patent: 6175530 (2001-01-01), Theron et al.

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