Method for repairing plasma damage after spacer formation...

Details Method for repairing plasma damage after spacer formation... Method for repairing plasma damage after spacer formation...

2006-11-07

2006-11-07

Coleman, W. David (Department: 2823)

Semiconductor device manufacturing: process

Chemical etching

Combined with coating step

C438S704000, C257SE21626

Reexamination Certificate

active

07132368

ABSTRACT:
A method for processing integrated circuit memory devices. The method includes supporting a partially completed substrate, the substrate comprising a plurality of MOS gate structures. Each of the gate structures has substantially vertical regions that define sides of the gate structures. The method forms a conformal dielectric layer overlying the gate structures. The conformal dielectric layer has a predetermined thickness of material that covers each of the gate structures including vertical regions. The method also forms sidewall spacers on the sides of the gate structures from the conformal dielectric layer using an anisotropic etching process and exposes a portion of the substrate region during the formation of the sidewall spacers using the anisotropic etching process to cause physical damage (e.g., plasma damage, cracks) to a portion of the exposed portion of the substrate. The method smoothes exposed portions of the sidewall spacers and exposed portions of the substrate using at least a plasma treatment process including an isotropic etching component to the exposed portion of the substrate and sidewall spacers on the sides of the gate structures whereupon the exposed portion of the sidewall spacers result to a predetermined surface roughness value.

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patent: 2005/0215008 (2005-09-01), Orlowski et al.

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