Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2000-01-14
2001-09-18
Nelms, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S210130
Reexamination Certificate
active
06292414
ABSTRACT:
BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
The invention relates to a method for repairing defective memory cells of an integrated semiconductor memory.
The U.S. Pat. No. 5,410,687 describes such a method. Individual memory cells of a memory are tested, wherein the memory cells are situated at crossover points of rows and columns. For each column and each row, the memory has a defect counter in which the defects that are detected for this column or row, respectively, are summed. Once all of the memory cells have been tested, defective memory cells are repaired through the use of redundant column and row lines on the basis of the information items stored in the defect counters. The defect counters required for its implementation require a relatively large amount of space.
The U.S. Pat. No. 5,206,583 describes an integrated circuit which has fuses for a permanent programming of redundant elements. The integrated circuit furthermore has reversibly programmable elements in the form of latches, which are connected in parallel with the fuses and serve, for test purposes, for reversibly programming the redundant elements.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a method for repairing defective memory cells of an integrated memory which overcomes the above-mentioned disadvantages of the heretofore-known methods of this general type and for which the necessary hardware components require the smallest possible area.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for repairing defective memory cells connected to respective row lines and respective column lines in an integrated semiconductor memory. The method includes the steps of providing at least two submethods for testing memory cells in an integrated semiconductor memory and repairing defective ones of the memory cells, each of the at least two submethods performing a successive testing of the memory cells and, after ascertaining a defect of a given one of the memory cells and prior to checking a further one of the memory cells, replacing one of a row line and a column line connected to the given one of the memory cells by programming one of a plurality of redundant lines including redundant row lines and redundant column lines, the at least two submethods differing in terms of an order of checking the memory cells and in terms of selecting a given one of the plurality of redundant lines for the purpose of replacing one of the row line and the column line by programming the one of the plurality of redundant lines; calling one of the at least two submethods and terminating the one of the at least two submethods with a defect-signature, the defect-signature containing information about a number of checked memory cells and a number of one of programmed ones of the plurality of redundant lines and remaining ones of the plurality of redundant lines; and subsequently, depending on the defect-signature, calling another one of the at least two submethods, the another one of the at least two submethods initially performing a step selected from the group consisting of entirely canceling, partially canceling, and not canceling the programming of at least one of the plurality of redundant lines.
In accordance with another mode of the invention, at least one of the submethods is called until all of the memory cells have been checked and repaired, or until the integrated semiconductor memory is identified as irreparable.
In accordance with yet another mode of the invention, the defect-signature includes at least one parameter having a value that is changeable during an execution time of the method for repairing defective memory cells.
In accordance with a further mode of the invention, the value of the at least one parameter is transferred to one of the at least two submethods following a currently active one of the at least two submethods.
In accordance with yet a further mode of the invention, the at least two submethods include the steps of programming a given number of the redundant lines including a specific one of the redundant lines for repairing a specific one of the memory cells; subsequently canceling the programming of at least the specific one of the redundant lines in the event of ascertaining a further defect; and programming the specific one of the redundant lines for repairing a defect of one of the memory cells other than the specific one of the memory cells.
In accordance with an added mode of the invention, a first one of the at least two submethods includes the steps of canceling programmings of redundant lines performed during a preceding execution of at least one of the at least two submethods; testing the memory cells for defects in a row by row manner, beginning with a start address; in the event of ascertaining a defect of a currently tested memory cell, replacing a relevant column line by one of the redundant column lines if a number of programmed redundant column lines does not exceed a limit value; in the event of exceeding the limit value, cancelling all programmings of redundant column lines effected on account of defects ascertained in a relevant row line; and replacing the relevant row line by one of the redundant row lines.
In accordance with another mode of the invention, the first one of the at least two submethods is terminated if all of the memory cells have been repaired or, if, after a further defect has been ascertained and the limit value is exceeded, all of the redundant row lines have already been programmed.
In accordance with yet another mode of the invention, the limit value is changed during an execution time of the first one of the at least two submethods.
In accordance with an added mode of the invention, the at least two submethods include a first submethod and a second submethod, and the second submethod includes the steps of testing the memory cells beginning with a start address; after all of the redundant lines have been programmed, canceling the programming of one of the redundant lines, in the event of a further defect being ascertained; subsequently testing the memory cells again, beginning with the start address; reversing the canceling of the programming of the one of the redundant lines, if, during the step of subsequently testing, a defect is ascertained and the defect is located before the further defect in address terms; subsequently, with regard to the programming of another one of the redundant lines, repeating the steps of canceling the programming, testing the memory cells again and reversing the canceling; and repairing the further defect using a redundant line having become free due to the canceling of the programming, if, after the canceling of the programming of one of the redundant lines, no defect located before the further defect in address terms is ascertained during the subsequent testing of the memory cells.
In accordance with another mode of the invention, the second submethod is terminated if all of the memory cells have been repaired or, if, after the further defect has been ascertained, the successive canceling of the programming of all of the redundant lines does not allow a repair of all of the defects identified.
The column lines may for example be bit lines and the row lines may for example be word lines of the integrated memory. In other exemplary embodiments, the column lines may also be word lines and the row lines may also be bit lines of the memory.
The method according to the invention has the advantage that defect counters for each column line and row line to be tested are not necessary since a defect is repaired in each case after it has been ascertained. In order to achieve more extensive optimization of the repair to be carried out, the method comprises at least two different submethods or partial methods. The submethods are configured differently and called or invoked successively, with the result that the respective specific advantages of the submethods contribute, in combination, to an improved result of the repair to be carried out, compared
Kaiser Robert
Schamberger Florian
Greenberg Laurence A.
Infineon - Technologies AG
Le Thong
Lerner Herbert L.
Nelms David
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