Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Patent
1998-03-30
2000-05-16
Le, Dieu-Minh T.
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
714 6, 714710, 714711, G06F 1116, G06F 1200
Patent
active
060651342
ABSTRACT:
A method provides an on-chip repair technique to fix defective row or I/O memory lines in an ASIC memory array with redundancy row or I/O memory lines. The method employs progressive urgency and dynamic repair schemes to optimize the allotted time for repairing defective row and I/O memory lines. Progressive urgency scheme increases the need to repair relative to the available redundancy row or I/O memory lines over the entire repairing time. Dynamic repair executes a mandatory-row or a mandatory-I/O repair as defective row or I/O memory lines are detected. In addition, a recurrence error reroutes the address location of a redundancy memory line to another address location of another redundancy memory line in the event that such redundancy memory line itself is defective, and thus requires further repair.
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Anderson Thomas P.
Bair Owen S.
Kablanian Adam
Le Chuong T.
Soundararajan Saravana
Le Dieu-Minh T.
LSI Logic Corporation
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