Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – Insulative material deposited upon semiconductive substrate
Reexamination Certificate
2002-08-29
2004-01-13
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
Insulative material deposited upon semiconductive substrate
C438S954000, C438S287000, C438S257000
Reexamination Certificate
active
06677255
ABSTRACT:
FIELD OF THE INVENTION
The invention relates in general to a method of fabricating a semiconductor device, and, more specifically, to a method of removing fences after etching without reducing the thickness of a dielectric layer.
BACKGROUND
In general, a flash memory device includes a floating gate formed over a first dielectric layer, which is formed over a semiconductor substrate, a control gate, and a second dielectric layer formed between the floating and control gates. The second dielectric layer is often comprised of a bottom silicon oxide layer, middle silicon nitride layer, and top silicon oxide layer. Such a structure is known as an oxide-nitride-oxide (“ONO”) structure. The resulting staked dielectric layer provides superior electrical isolation between the floating and control gates. However, an ONO structure may also be used for the first dielectric layer, and generally in conventional transistors or other types of memories.
During the manufacturing process relating to the ONO structure, a photoresist (“PR”) is usually provided over the top silicon oxide layer. After the PR is defined and patterned, an etch step, usually dry etch, follows to remove certain portions of the ONO structure. The etching process often results in the formation of ONO fences, or residues, that may adversely affect the subsequent manufacturing steps. Because the ONO fences remain behind after the PR is stripped, a subsequent cleaning process is used to remove the fences.
Conventionally, a HF or a SC-1 solution, which is typically a 5:1:1 solution of water, hydrogen peroxide, and ammonium hydroxide, is used. However, the top oxide layer, which is typically relatively thin, becomes even thinner due to the chemical cleaning process. The process may decrease the effective oxide thickness (“EOT”) of the ONO structure. If the EOT is overly decreased, the thickness between the floating gate and control gate may be decreased to such an extent so as to adversely affect the performance of the completed semiconductor device. For example, leakage currents may occur because of the reduction in the EOT of the ONO layer.
SUMMARY OF THE INVENTION
In accordance with the invention, there is provided a method of manufacturing a semiconductor device that includes providing a wafer substrate, providing an insulator over the wafer substrate, depositing a first polysilicon layer over the insulator, forming a layer of stacked oxide-nitride-oxide layer over the first polysilicon layer, depositing a second silicon layer over the layer of stacked oxide-nitride-oxide layer, providing a layer of photoresist over the second silicon layer, patterning and defining the photoresist layer, etching the second silicon layer and stacked oxide-nitride-oxide layer unmasked by the photoresist, removing the photoresist layer, providing a cleaning solution to the stacked oxide-nitride-oxide layer with the second silicon layer as a mask, and depositing a third layer of polysilicon over the second silicon layer.
Also in accordance with the present invention, there is provided a method of manufacturing a semiconductor device that includes providing a first layer, forming a layer of stacked oxide-nitride-oxide layer over the first layer, depositing a first silicon layer over the layer of stacked oxide-nitride-oxide layer, providing a layer of photoresist over the first silicon layer, patterning and defining the photoresist layer, etching the first silicon layer and stacked oxide-nitride-oxide layer unmasked by the photoresist, removing the photoresist layer, providing a cleaning solution to the stacked oxide-nitride-oxide layer with the first silicon layer as a mask, and depositing a second layer of polysilicon over the first silicon layer to form a combined silicon layer.
Additional objects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the appended claims.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
REFERENCES:
patent: 6043005 (2000-03-01), Haq
patent: 6127277 (2000-10-01), DeOrnellas et al.
patent: 6242350 (2001-06-01), Tao et al.
patent: 6277762 (2001-08-01), Hwang
patent: 6436766 (2002-08-01), Rangarajan et al.
patent: 6486029 (2002-11-01), Foote et al.
Chen Kuang-Chao
Shih Hsueh-Hao
Elms Richard
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Macroniox International Co., Ltd.
Owens Beth E.
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