Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Patent
1997-07-31
1999-10-26
Beausoliel, Jr., Robert W.
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
G06F 1100
Patent
active
059745649
ABSTRACT:
A computer system includes a memory controller that interfaces a memory requester with a memory device that may include defective memory cells. For each of plural memory blocks, defective bit sets having one or more defective memory cells are identified. A bit set error map is created and stored which identifies the defective bit sets of each of the memory blocks. In response to receiving from the memory requester a request for access to a requested storage location of the memory device, a determination is made from the error map whether the storage location is in a memory block that includes one or more defective bit sets. If the error map indicates that the requested storage location is in a memory block with one or more defective bit sets, then a determination is made from the error map which of the bit sets are defective. To execute the memory access request, the memory controller accesses the non-defective bit sets to which the defective bit sets have been mapped.
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Beausoliel, Jr. Robert W.
Elmore Stephen C.
Micron Electronics Inc.
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