Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
2002-01-24
2003-12-23
Kim, Matthew (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C711S106000, C365S185330, C365S185020, C365S185120, C365S222000
Reexamination Certificate
active
06668303
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to the field of semiconductor memory devices, and more particularly to non-volatile memories. Still more particularly, the invention relates to electrically erasable and programmable non-volatile memories, such as Flash memories.
2. Background of the Invention
As known, in Flash non-volatile memories data are written (programmed) by means of hot electron injection into floating-gate electrodes (briefly, floating gates) of the memory cells. To erase data, electrons are extracted from the floating gates of the memory cells by means of the mechanism known as Fowler-Nordheim tunnelling at high electric fields, giving rise to a Fowler-Nordheim current.
In conventional Flash memories, only the whole two-dimensional array (also called matrix) of memory cells or, where memory sectors are provided, only a whole memory sector can be erased at a time. All the memory cells of the matrix or memory sector to be erased are submitted to an erase voltage
V
GB
=V
G
−V
B
where V
G
is for example a negative voltage (e.g., ranging from −8V to −9V) applied simultaneously to all the rows (word lines) of the matrix or memory sector, that is, to the memory cells' control-gate electrode (briefly, control gate), and V
B
is a positive voltage (e.g., ranging from 8V to 9V) applied to the common substrate or bulk electrode of the memory cells of the matrix or memory sector are formed. Starting from an initial value, the erase voltage is progressively increased (in absolute value) until by progressive extraction of electrons from the floating gates of the threshold voltage of all the memory cells is brought below a prescribed reference value, chosen to assure a proper margin compared to the standard memory read conditions.
The global character of the erase operation is a significant disadvantage of conventional Flash memories. In fact, even if memory sectors are provided, the minimum memory sector size that can be practically achieved, at a reasonable cost in terms of semiconductor chip area, is of some Kbytes. This means that when even a single data Byte or word belonging to a given memory sector is to be modified, the whole memory sector, that is some Kbytes of memory space, must be erased and then rewritten.
This limits the otherwise highly desirable use of Flash memories in those applications which require often to modify single data Bytes or words.
As a solution to this problem, it could be envisaged that in an erase operation only one word line (more generally, only a subset of the set of word lines making up the memory matrix or sector) is biased to a negative voltage V
selG
of, e.g., −8 V to −9 V, while the remaining word lines of the matrix or memory sector are biased to an erase inhibition voltage V
deselG
equal to ground or, preferably, intermediate between ground and the voltage V
B
. In this way, only the memory cells belonging to the selected word line(s) are submitted to the erase voltage V
GB
, while for the memory cells belonging to the non-selected word lines the electric field across the gate oxide thereof is substantially reduced not to trigger the Fowler-Nordheim tunneling.
As a result of the above solution, which requires a suitable modification of the conventional row address decoder and row selection circuits, the Flash memory can have a finer granularity in erasing, equal to one word line (or a subset of word lines). Defining as “memory page” the elementary memory unit that can be individually erased, that is, one word line (or a subset of word lines), the memory device can be called “Page Erasable ROM” or “PEROM”.
A problem affecting the PEROM is that, when a memory page is to be erased, the memory cells not belonging to that memory page but however belonging to the same memory sector (or to the memory matrix if no memory sectors are provided with) are disturbed. In fact, even if the gate-bulk voltage (V
deselG
-V
B
) to which such memory cells are subjected is not sufficient to erase them, such a voltage is however favorable to the extraction of electrons from the floating gates thereof, and thus to a small reduction of the threshold voltages. Considering that any given memory page can be erased and rewritten many thousands of times, some memory cells, even if not belonging to the word lines selected for erasure, may at a given time lose the datum stored therein.
SUMMARY OF THE INVENTION
In view of the state of the art described, it is an object of the present invention to provide a method of refreshing the datum stored in each memory cell, so as to avoid spurious erasure thereof caused by disturbances induced thereon during the erase operations on other memory cells.
According to the present invention, these and other objects are achieved by a method for refreshing data stored in an electrically erasable and programmable non-volatile semiconductor memory comprising at least one two-dimensional array of memory cells containing a plurality of individually erasable and programmable memory pages, providing for:
each time a request to modify a content of a memory page is received by the memory, modifying the content of said memory page and submitting a portion of the two-dimensional array to a refresh procedure, the refresh procedure comprising detecting memory cells of that memory portion that have partially lost a respective datum stored therein and reprogramming the datum in the detected memory cells.
As a result of the method according to the invention, it is assured that all the memory cells are periodically subjected to a data refresh procedure preventing the data stored therein to get lost due to disturbances induced on such memory cells during erase operations on different memory cells of the memory matrix or of the same memory sector. Such a refresh operation is substantially transparent for the user, since it can be carried out each time a request to modify a memory page is received by the memory, preferably after completion of this operation.
REFERENCES:
patent: 5239505 (1993-08-01), Fazio et al.
patent: 5574684 (1996-11-01), Tomoeda
patent: 5652720 (1997-07-01), Aulus et al.
patent: 5765185 (1998-06-01), Lambrache et al.
patent: 6026024 (2000-02-01), Odani et al.
patent: 6108241 (2000-08-01), Chevallier
patent: 6166959 (2000-12-01), Gupta et al.
patent: 6493270 (2002-12-01), Chevallier
patent: 2002/0149986 (2002-10-01), Wong
patent: 0 718 849 (1996-06-01), None
patent: 00/16338 (2000-03-01), None
Shigeru Atsumi et al. “A 16 MB Flash EEPROM with a new self-data-refresh scheme for a sector erase operation” IEICE Transactions of Electronics. 1 May 1994.*
Shigeru Atsumi et al.; “A 16-Mb Flash EEPROM with a New Self-Data-Refresh Scheme for a Sector Erase Operation”, vol. E77-C, No. 5 dated 1 May 1994, pp. 791-798, XP000459519.
Allen Dyer Doppelt Milbrath & Gilchrist, P.A.
Anderson Matthew D.
Jorgenson Lisa K.
Kim Matthew
STMicroelectronics S.r.l.
LandOfFree
Method for refreshing stored data in an electrically... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for refreshing stored data in an electrically..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for refreshing stored data in an electrically... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3182800